FPGA Based Big Data Accelerator Design in Teaching Computer Architecture and Organization
In the past few years big data applications are becoming diverse and ubiquitous. There is a renewed interest in teaching senior level students to be professional in accelerator based computer architecture design and engineering. However, it poses a significant challenge to tutor the students with sufficient knowledge and practical skills in this area. In this paper, we propose a big data accelerator design project implemented on field-programmable gate array (FPGA) in teaching a computer architecture and organization course. The experimental system is carried out on a heterogeneous architecture using Xilinx Virtex 5 development boards. To achieve a modular accelerator implementation, several milestones are set to facilitate the on-time complete of the project. With the assistance of the FPGA-based experiment, most students have obtained a much more comprehensive understanding of the processor architecture and the accelerator design paradigm. Student feedback and survey illustrates the effectiveness and popularity of the FPGA-based project with milestones over simulation based experiments.
KeywordsApplications in subject areas Simulations FPGA
This work is partially supported by the National Key Research and Development Program of China (under Grant 2017YFA0700900), Anhui Provincial Natural Science Foundation (No. 1608085QF12), Jiangsu Provincial Natural Science Foundation (No. BK20181193), Youth Innovation Promotion Association CAS (No. 2017497), and Fundamental Research Funds for the Central Universities (WK2150110003).
- 3.Han, S., et al.: ESE: efficient speech recognition engine with sparse LSTM on FPGA. In: FPGA, pp. 75–84 (2017)Google Scholar
- 5.Wang, C., Gong, L., Yu, Q., Li, X., Xie, Y., Zhou, X.: DLAU: a scalable deep learning accelerator unit on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3), 513–517 (2017)Google Scholar
- 7.Lu, S.L.L., Yiannacouras, P., Suh, T., Kassa, R., Konow, M.: A desktop computer with a reconfigurable pentium®. ACM Trans. Reconfigurable Technol. Syst. (TRETS) 1(1), 5 (2008)Google Scholar
- 21.Feist, T.: Vivado design suite. White Paper 5 (2012)Google Scholar
- 22.O’Loughlin, D., Coffey, A., Callaly, F., Lyons, D., Morgan, F.: Xilinx Vivado high level synthesis: case studies (2014)Google Scholar