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Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems

  • Tobias DörrEmail author
  • Timo Sandmann
  • Florian Schade
  • Falco K. Bapp
  • Jürgen Becker
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11444)

Abstract

Processor-based digital systems are increasingly being used in safety-critical environments. To meet the associated safety requirements, these systems are usually characterized by a certain degree of redundancy. This paper proposes a concept to introduce a redundant processor on demand by using the partial reconfiguration capability of modern FPGAs. We describe a possible implementation of this concept and evaluate it experimentally. The evaluation focuses on the fault handling latency and the resource utilization of the design. It shows that an implementation with 32 KiB of local processor memory handles faults within 0.82 ms and, when no fault is present, consumes less than 46% of the resources that a comparable static design occupies.

Keywords

Fail-operational system Graceful degradation Partial reconfiguration Dynamic redundancy Simplex architecture Fallback processor Multiprocessor system-on-chip Soft-core processor 

Notes

Acknowledgements

This work was funded by the German Federal Ministry of Education and Research (BMBF) under grant number 01IS16025 (ARAMiS II). The responsibility for the content of this publication rests with the authors.

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Karlsruhe Institute of Technology (KIT)KarlsruheGermany

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