ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures

  • Ludovica Bozzoli
  • Luca SterponeEmail author
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11444)


Recently, the usage of the reconfigurable computing devices has seen a sharp increase in many application fields. Several reconfigurable architectures have been proposed in the last decades, with different levels of granularity and complexity and SRAM-based Field Programmable Gate Array (FPGA) remains the target support to develop reconfigurable architectures. However, even if FPGA is an established technology, it is not fully optimized for detailed partial run time reconfiguration. In fact, FPGAs reconfiguration granularity is large, even if single resources are configured by few bits, since the amount of data to be re-loaded inside the configuration memory for small changes is huge. Considering that the major bottleneck of reconfiguration is the excessive reconfiguration time, which is proportional to the number of bits to be reconfigured, when reconfiguration involves few basic resources, such architecture leads to a considerable overhead.

In this paper, we propose a new reconfigurable computing architecture that implement distributed reconfiguration at the lowest granularity to maximize flexibility and scalability. This is obtained providing to the basic reconfigurable functional unit the ability to reconfigure itself and the neighbor units. In fact, each cell, beside functioning as Logic, Memory and Connectivity can also trigger reconfiguration for itself and for given portion of the array of cells. To show the feasibility and the advantages of our idea, we designed and implemented a Reconfigurable Multipotent Cell, ReM. The results obtained with the implementation of benchmark circuits on this architecture confirm the advantages in terms of reconfiguration time.


FPGA Reconfigurable architectures Reconfiguration time Reconfigurable array 


  1. 1.
    Tessier, R., Pocek, K., DeHon, A.: Reconfigurable computing architectures. Proc. IEEE 103(3), 332–354 (2015)CrossRefGoogle Scholar
  2. 2.
    Ul-Abdin, Z., Svensson, B.: Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing. Microprocess. Microsyst. Embed. Hardw. Des. 33, 161–178 (2009)CrossRefGoogle Scholar
  3. 3.
    Hartenstein, R.: Trends in reconfigurable logic and reconfigurable computing. In: 9th International Conference on Electronics, Circuits and Systems, Dubrovnik, Croatia, vol. 2, pp. 801–808 (2002)Google Scholar
  4. 4.
    Xilinx User Guide: 7 Series FPGAs Configuration. UG470, v1.11, pp. 1–176, 27 September 2016Google Scholar
  5. 5.
    Bozzoli, L., Sterpone, L.: COMET: a configuration memory tool to analyze, visualize and manipulate FPGAs bitstream. In: ARCS Workshop 2018, 31st International Conference on Architecture of Computing Systems, Braunschweig, Germany, pp. 1–4 (2018)Google Scholar
  6. 6.
    Hai, Y., Zhao, X., Liu, Y.: Reconfigurable computing availability and developing trends. In: 2015 11th International Conference on Computational Intelligence and Security, CIS, Shenzhen, pp. 138–141 (2015)Google Scholar
  7. 7.
    DeHon, A., Wawrzynek, J.: Reconfigurable computing: what, why, and implications for design automation. In: Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), New Orleans, LA, USA, pp. 610–615 (1999)Google Scholar
  8. 8.
    Singh, H., Lee, M.H., Lu, G., Kurdahi, F.J., Bagherzadeh, N., Filho, E.M.C.: MorphoSys: an integrated reconfigurable system for data-parallel computation-intensive applications. IEEE Trans. Comput. 49, 465–481 (2000)CrossRefGoogle Scholar
  9. 9.
    DAPDNA-2 Dynamically Reconfigurable Processor product brochure. IPFlexInc., 13 March 2007Google Scholar
  10. 10.
    XPP III Processor Overview: (XPP-III_overview_WP.pdf), 13 March 2008Google Scholar
  11. 11.
    Mirsky, E., DeHon, A.: MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. In: Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, pp. 157–166, April 1996Google Scholar
  12. 12.
    Taylor, M.B., et al.: Evaluation of the RAW microprocessor: an exposed-wire-delay architecture for ILP and streams. In: Proceedings of 31st International Symposium on Computer Architecture, ISCA (2004)Google Scholar
  13. 13.
    picoArray: ASIC processing power with DSP flexibility, PC102 datasheet, 8 December 2004Google Scholar
  14. 14.
    Walker, J.A., Trefzer, M.A., Bale, S.J., Tyrrell, A.M.: PAnDA: a reconfigurable architecture that adapts to physical substrate variations. IEEE Trans. Comput. 62(8), 1584–1596 (2013)MathSciNetCrossRefGoogle Scholar
  15. 15.
    Langeheine, J., Becker, J., Folling, S., Meier, K., Schemmel, J.: A CMOS FPTA chip for intrinsic hardware evolution of analog electronic circuits. In: Proceedings of Third NASA/DoD Workshop on Evolvable Hardware, EH-2001, Long Beach, CA, USA, pp. 172–175 (2001)Google Scholar
  16. 16.
    Neumann, B., von Sydow, T., Blume, H., Noll, T.G.: Design flow for embedded FPGAs based on a flexible architecture template. In: 2008 Design, Automation and Test in Europe, Munich, pp. 56–61 (2008)Google Scholar
  17. 17.
    MENTA eFPGA-augmented RISC CPUs (website).
  18. 18.
    Heiner, J., Collins, N., Wirthlin, M.: Fault tolerant ICAP controller for high-reliable internal scrubbing. In: IEEE Aerospace Conference, pp. 1–10 (2008)Google Scholar
  19. 19.
    Sterpone, L., Bozzoli, L.: Fast partial reconfiguration on SRAM-based FPGAs: a frame-driven routing approach. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P.C. (eds.) ARC 2018. LNCS, vol. 10824, pp. 319–330. Springer, Cham (2018). Scholar
  20. 20.
    Sterpone, L., Du, B.: SET-PAR: place and route tools for the mitigation of single event transients on flash-based FPGAs. In: Sano, K., Soudris, D., Hübner, M., Diniz, P.C. (eds.) ARC 2015. LNCS, vol. 9040, pp. 129–140. Springer, Cham (2015). Scholar
  21. 21.
    Corno, F., Reorda, M.S., Squillero, G.: RT-level ITC’99 benchmarks and first ATPG results. IEEE Des. Test Comput. 17(3), 44–53 (2000)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Politecnico di TorinoTurinItaly

Personalised recommendations