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An FPGA Based Hardware Accelerator for Classification of Handwritten Digits

  • R. Gautham Sundar RamEmail author
  • Nitin Chaturvedi
  • Sumeet Saurav
  • Sanjay Singh
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 940)

Abstract

Over the past few years, Convolutional Neural Networks (CNNs) have provided major breakthroughs in fields such as computer vision and natural language processing, resulting in a rise in the adoption of CNNs with increased levels of complexity. Consequently, the need for fast and power efficient processing of such networks has become critically important. Conventional hardware solutions, namely CPUs and GPUs, fail to address these requirements as CPUs are not suited for processing massively parallel multiply and accumulate (MAC) operations and GPUs are not power efficient. However, Field Programmable Gate Arrays (FPGAs) have emerged as a promising alternative due to their extensive programmability, ease of executing parallel operations and wide interfacing capabilities. In this paper, we have designed a hardware accelerator for speeding up the inference phase of LeNet–5 to enable faster classification of handwritten digits. We employ software quantization for ease of implementation on FPGAs, and partial pipelining to process the various layers of a typical CNN. Targeting the Xilinx Zynq-7000 SoC, we report a speedup improvement of at least 4.7x and power efficiency improvement of 32x compared to similar works.

Keywords

FPGA CNN Accelerator LeNet–5 

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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • R. Gautham Sundar Ram
    • 1
    Email author
  • Nitin Chaturvedi
    • 1
  • Sumeet Saurav
    • 2
  • Sanjay Singh
    • 2
  1. 1.Department of EEEBirla Institute of Technology and SciencePilaniIndia
  2. 2.Cognitive Computing GroupCSIR-CEERIPilaniIndia

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