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Circuit and Layout Level Validation

  • Mauro SantosEmail author
  • Jorge Guilherme
  • Nuno Horta
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 558)

Abstract

This chapter will present the major building blocks that comprise the demonstrator prototype. Except for the I/O pads there was no use of ready-made cells, everything had to be designed from schematic capture to the final layout. Table 5.1 summarizes the logic cells and logic blocks that have been designed. Most of the blocks have been used in the design of the test chip however some blocks such as the static flip-flop with reset and the 10 bit frequency counter have not been used. The unused blocks are leftovers from previous iterations of the test chip where different testing methodologies were being evaluated.

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Synopsys Portugal LdaPorto SalvoPortugal
  2. 2.Instituto Superior TécnicoInstituto TelecomunicaçõesLisbonPortugal
  3. 3.Instituto Superior TécnicoInstituto TelecomunicaçõesLisbonPortugal

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