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Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI

  • Kimiyoshi UsamiEmail author
  • Shunsuke Kogure
  • Yusuke Yoshida
  • Ryo Magasaki
  • Hideharu Amano
Conference paper
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 500)

Abstract

Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) at pMOS transistors in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip showed that the chip applying the LSL approach correctly operates at VDDL = 0.6 V and VDDH = 1.2 V under 2 V pMOS RBB while suppressing the static dc current in the VDDH domain. We also demonstrate that adaptive RBB control for pMOS can maintain effectiveness of this approach under process and temperature variations.

Keywords

Level shifter Multi-VDD design Body bias control FD-SOI Low power Variations 

Notes

Acknowledgment

This work was partially supported by JSPS KAKENHI S Grant Number 25220002. This work was supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc. This presentation was supported by SIT Research Center for Green Innovation.

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Copyright information

© IFIP International Federation for Information Processing 2019

Authors and Affiliations

  • Kimiyoshi Usami
    • 1
    Email author
  • Shunsuke Kogure
    • 1
  • Yusuke Yoshida
    • 1
  • Ryo Magasaki
    • 1
  • Hideharu Amano
    • 2
  1. 1.Shibaura Institute of TechnologyTokyoJapan
  2. 2.Keio UniversityYokohamaJapan

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