Embedding CCSL into Dynamic Logic: A Logical Approach for the Verification of CCSL Specifications

  • Yuanrui Zhang
  • Hengyang Wu
  • Yixiang Chen
  • Frédéric MalletEmail author
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 1008)


The Clock Constraint Specification Language (CCSL) is a clock-based specification language for capturing causal and chronometric constraints between events in Real-Time Embedded Systems (RTESs). Due to the limitations of the existing verification approaches, CCSL lacks a full verification support for ‘unsafe CCSL specifications’ and a unified proof framework. In this paper, we propose a novel verification approach based on theorem proving and SMT-checking. We firstly build a logic called CCSL Dynamic Logic (CDL), which extends the traditional dynamic logic with ‘signals’ and ‘clock relations’ as primitives, and with synchronous execution mechanism for modelling RTESs. Then we propose a sound and relatively complete proof system for CDL to provide the verification support. We show how CDL can be used to capture RTES and verify CCSL specifications by analyzing a simple case study.


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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Yuanrui Zhang
    • 1
  • Hengyang Wu
    • 1
  • Yixiang Chen
    • 1
  • Frédéric Mallet
    • 2
    Email author
  1. 1.MoE Engineering Research Center for Software/Hardware Co-design Technology and ApplicationEast China Normal UniversityShanghaiChina
  2. 2.Université Cote d’Azur, I3S, CNRS, InriaSophia AntipolisFrance

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