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An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding

  • Paolo Selvo
  • Maurizio Masera
  • Riccardo Peloso
  • Guido Masera
  • Muhammad Shafique
  • Maurizio MartinaEmail author
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 573)

Abstract

Sum of Absolute Differences (SAD) is one of the most time consuming tasks in video coding. This paper proposes an architecture to compute the SADs for all the different block sizes required by the High Efficiency Video Coding (HEVC) standard. Moreover, the Partial Distortion Elimination (PDE), clock gating and a low leakage technology enable high power/energy reductions/savings over the state of the art.

Keywords

VLSI architecture Motion estimation HEVC 

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Paolo Selvo
    • 1
  • Maurizio Masera
    • 1
  • Riccardo Peloso
    • 1
  • Guido Masera
    • 1
  • Muhammad Shafique
    • 2
  • Maurizio Martina
    • 1
    Email author
  1. 1.Department of Electronics and TelecommunicationsPolitecnico di TorinoTurinItaly
  2. 2.Institute of Computer EngineeringVienna University of Technology (TU Wien)ViennaAustria

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