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A Background-Calibrated Digital Subsampling Polar Transmitter

  • Nereo Markulic
  • Kuba Raczkowski
  • Jan Craninckx
  • Piet Wambacq
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

In this chapter we present a transmitter, implemented in 28 nm CMOS, which incorporates a low-noise subsampling PLL for phase modulation (PM) and a harmonic rejection mixed inverse class-D digital power amplifier for amplitude modulation (AM). Unlike in a classical polar transmitter, the amplitude modulation happens within the phase lock in this system. As shown throughout the chapter, this specific feature enables background AM-to-AM nonlinearity cancellation, and inherits suppression of AM-to-PM induced distortion. To emphasize this specific property which is a consequence of direct sampling at the transmitter output, we name the architecture subsampling polar transmitter (SSPTX). The chip operates from a 0.9 V supply at 5.5 GHz with 2.5 MHz BW and 1024 QAM with average 1.1 dBm output power, and total power consumption of 50 mW. The proposed SSPTX enables extreme spectral efficiency, outperforming similar art in the field. The explored architecture reveals new opportunities in digital TX solutions for next generation wireless links.

Keywords

Polar transmitter Transmitter Subsampling polar transmitter Subsampling PLL Digital-to-time converter Background AM-to-AM cancellation AM-to-PM filtering 

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Nereo Markulic
    • 1
  • Kuba Raczkowski
    • 1
  • Jan Craninckx
    • 1
  • Piet Wambacq
    • 1
  1. 1.IMECLeuvenBelgium

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