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A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation

  • Nereo Markulic
  • Kuba Raczkowski
  • Jan Craninckx
  • Piet Wambacq
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

In this chapter, we present a DTC-based fractional-N subsampling PLL that operates without performance gap between integer-N and fractional-N modes. This is achieved thanks to the digital background cancellation of nonlinearities in the PLL phase-error comparison path. This −247-dB FOM PLL is further enhanced for two-point, wideband phase modulation, achieving <−40-dB EVM around a 10-GHz carrier during 10-Mb/s GMSK modulation. Analog nonidealities, such as gain imbalance or nonlinearity in the digital-to-modulated phase conversion, are background cancelled, ensuring robust operation with PVT. This system demonstrates state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Nereo Markulic
    • 1
  • Kuba Raczkowski
    • 1
  • Jan Craninckx
    • 1
  • Piet Wambacq
    • 1
  1. 1.IMECLeuvenBelgium

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