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Impact of the Trap Attributes on the Gate Leakage Mechanisms in a 2D MS-EMC Nanodevice Simulator

  • Cristina Medina-BailonEmail author
  • Toufik Sadi
  • Carlos Sampedro
  • Jose Luis Padilla
  • Luca Donetti
  • Vihar Georgiev
  • Francisco Gamiz
  • Asen Asenov
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11189)

Abstract

From a modeling point of view, the inclusion of adequate physical phenomena is mandatory when analyzing the behavior of new transistor architectures. In particular, the high electric field across the ultra-thin insulator in aggressively scaled transistors leads to the possibility for the charge carriers in the channel to tunnel through the gate oxide via various gate leakage mechanisms (GLMs). In this work, we study the impact of trap number on gate leakage using the GLM model, which is included in a Multi-Subband Ensemble Monte Carlo (MS-EMC) simulator for Fully-Depleted Silicon-On-Insulator (FDSOI) field effect transistors (FETs). The GLM code described herein considers both direct and trap-assisted tunneling. This work shows that trap attributes and dynamics can modify the device electrostatic characteristics and even play a significant role in determining the extent of GLMs.

Keywords

Gate leakage mechanism Direct tunneling Trap assisted tunneling MS-EMC FDSOI 

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Cristina Medina-Bailon
    • 1
    • 2
    Email author
  • Toufik Sadi
    • 3
  • Carlos Sampedro
    • 2
  • Jose Luis Padilla
    • 2
  • Luca Donetti
    • 2
  • Vihar Georgiev
    • 1
  • Francisco Gamiz
    • 2
  • Asen Asenov
    • 1
  1. 1.School of EngineeringUniversity of GlasgowGlasgowScotland, UK
  2. 2.Nanoelectronics Research GroupUniversidad de GranadaGranadaSpain
  3. 3.Department of Neuroscience and Biomedical EngineeringAalto UniversityAaltoFinland

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