Advertisement

Application of Parallel and Hybrid Metaheuristics for Graph Partitioning Problem

  • Zbigniew KokosińskiEmail author
  • Marcin Pijanowski
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11189)

Abstract

In this paper parallel and hybrid metaheuristics for graph partitioning are compared taking into account their efficiency in terms of a cost function and computation time. Seventeen methods developed on the basis of evolutionary algorithm, simulated annealing and tabu search are implemented and tested against graph instances computed on the basis of queen graphs from DIMACS repository and a class of random R–MAT graphs. These graphs are supposed to model a class of digital circuits being subject of decomposition into a given number of modules. In partitioning process several additional constraints have to be satisfied in order to enable composition of original circuits from subcircuits by means of VLSI/FPGA modules.

Keywords

Graph partitioning Circuit partitioning Parallel metaheuristics Hybrid metaheuristics Approximate algorithms DIMACS graphs R–MAT graphs 

Notes

Acknowledgements

This work was supported by the research grant No. E–3/611/2017/DS from Cracow University Technology.

References

  1. 1.
    Alba, E. (ed.): Parallel Metaheuristics: A new Class of Algorithms. Wiley-Interscience, New Jersey (2005)zbMATHGoogle Scholar
  2. 2.
    Chadha, A.: Benchmark Creation for Circuit Partitioning Algorithms. Gauging the Performance of Circuit Partitioning Algorithms. Lambert Academic Publishing (2015)Google Scholar
  3. 3.
    Chvátal, V.: Colouring the queen graphs. http://users.encs.concordia.ca/chvatal/queengraphs.html
  4. 4.
    Bhuvaneswari, M.C., Jagadeeswari, M.: Circuit partitioning for VLSI layout. In: Bhuvaneswari, M.C. (ed.) Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems, pp. 37–46. Springer, New Delhi (2015).  https://doi.org/10.1007/978-81-322-1958-3_3CrossRefGoogle Scholar
  5. 5.
    Chakrabarti, D., Zhan, Y., Faloutsos, C.: R-MAT: a recursive model for graph mining. In: Proceedings of 2004 SIAM International Conference Data Mining, 2004 (2004).  https://doi.org/10.1137/1.9781611972740_43
  6. 6.
  7. 7.
    Gil, C., Ortega, J., Montoya, M.G., Banos, R.: A Mixed Heuristic for Circuit Partitioning. Comput. Optim. Appl. 23, 321–340 (2002).  https://doi.org/10.1023/A:1020551011615MathSciNetCrossRefzbMATHGoogle Scholar
  8. 8.
    Bader, A., et al. (ed.): Graph Partitioning and Graph Clustering, 10th DIMACS Implementation Challenge, Atlanta, 12–13 February 2012, vol. 588. AMS, Contemporary Mathematics (2013)Google Scholar
  9. 9.
    Khang, A., Liening, J., Markov, I., Hu, J.: VLSI Physical Design: From Graph Partitioning to Timing Closure, pp. 33–54. Springer, Dordrecht (2011).  https://doi.org/10.1007/978-90-481-9591-6CrossRefGoogle Scholar
  10. 10.
    Kernighan, B.W., Lin, S.: An efficient heuristics procedure for partitioning graphs. Bell Syst. Tech. J. 49, 291–307 (1970)CrossRefGoogle Scholar
  11. 11.
    Kokosiński, Z., Bała, M.: Solving graph partitioning problems with parallel metaheuristics. In: Fidanova, S. (ed.) Recent Advances in Computational Optimization. SCI, vol. 717, pp. 89–105. Springer, Cham (2018).  https://doi.org/10.1007/978-3-319-59861-1_6CrossRefGoogle Scholar
  12. 12.
    Kozieł, S., Szczȩśniak, W.: Evolutionary algorithm for electronic system partitioning and its applications in VLSI design. In: Proceedings of 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, 5–8 September 1999, vol. 3, pp. 1412–1414 (1999)Google Scholar
  13. 13.
    Sadiq, S., Habib, Y.: Iterative Computer Algorithms with Applications in Engineering. Solving Combinatorial Optimization Problems. Wiley - IEEE Computer Society Press (2000)Google Scholar
  14. 14.
    Swethaa, R.R., Devi, K.A.S., Yousef, S.: Hybrid partitioning algorithm for area minimization in circuits. Procedia Comput. Sci. 48, 692–698 (2015).  https://doi.org/10.1016/j.procs.2015.04.203CrossRefGoogle Scholar
  15. 15.
    Szczȩśniak, W.: Application of adaptive circuit partitioning algorithms to reductions of interconnections length between elements of VLSI circuit. In: Proceedings of 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002, Dubrownik, Croatia, 15–18 September 2002.  https://doi.org/10.1109/ICECS.2002.1046259
  16. 16.
    Pseudocodes of algorithms from section 2.3. http://www.pk.edu.pl/~zk/pubs/NMA18.zip

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Faculty of Electrical and Computer EngineeringCracow University of TechnologyKrakówPoland

Personalised recommendations