Unleashing and Speeding Up Readers in Atomic Object Implementations

  • Chryssis Georgiou
  • Theophanis HadjistasiEmail author
  • Nicolas Nicolaou
  • Alexander A. Schwarzmann
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11028)


Providing efficient emulations of atomic read/write objects in asynchronous, crash-prone, message-passing systems is an important problem in distributed computing. Communication latency is a factor that typically dominates the performance of message-passing systems, consequently the efficiency of algorithms implementing atomic objects is measured in terms of the number of communication exchanges involved in each read and write operation. The seminal result of Attiya, Bar-Noy, and Dolev established that two pairs of communication exchanges, or equivalently two round-trip communications, are sufficient. Subsequent research examined the possibility of implementations that involve less than four exchanges. The work of Dutta et al. showed that for single-writer/multiple-reader (SWMR) settings two exchanges are sufficient, provided that the number of readers is severely constrained with respect to the number of object replicas in the system and the number of replica failures, and also showed that no two-exchange implementations of multiple-writer/multiple-reader (MWMR) objects are possible. Later research focused on providing implementations that remove the constraint on the number of readers, while having read and write operations that use variable number of communication exchanges, specifically two, three, or four exchanges.

This work presents two advances in the state-of-the-art in this area. Specifically, for SWMR and MWMR systems algorithms are given in which read operations take two or three exchanges. This improves on prior works where read operations took either (a) three exchanges, or (b) two or four exchanges. The number of readers in the new algorithms is unconstrained, and write operations take the same number of exchanges as in prior work (two for SWMR and four for MWMR settings). The correctness of algorithms is rigorously argued. The paper presents an empirical study using the NS3 simulator that compares the performance of relevant algorithms, demonstrates the practicality of the new algorithms, and identifies settings in which their performance is clearly superior.


  1. 1.
    NS3 network simulator.
  2. 2.
    Attiya, H., Bar-Noy, A., Dolev, D.: Sharing memory robustly in message passing systems. J. ACM 42(1), 124–142 (1996)CrossRefGoogle Scholar
  3. 3.
    Dutta, P., Guerraoui, R., Levy, R.R., Chakraborty, A.: How fast can a distributed atomic read be? In: Proceedings of PODC 2004, pp. 236–245 (2004)Google Scholar
  4. 4.
    Englert, B., Georgiou, C., Musial, P.M., Nicolaou, N., Shvartsman, A.A.: On the efficiency of atomic multi-reader, multi-writer distributed memory. In: Abdelzaher, T., Raynal, M., Santoro, N. (eds.) OPODIS 2009. LNCS, vol. 5923, pp. 240–254. Springer, Heidelberg (2009). Scholar
  5. 5.
    Georgiou, C., Nicolaou, N., Russell, A., Shvartsman, A.A.: Towards feasible implementations of low-latency multi-writer atomic registers. In: Proceedings of NCA 2011, pp. 75–82 (2011)Google Scholar
  6. 6.
    Georgiou, C., Nicolaou, N.C., Shvartsman, A.A.: On the robustness of (semi) fast quorum-based implementations of atomic shared memory. In: Taubenfeld, G. (ed.) DISC 2008. LNCS, vol. 5218, pp. 289–304. Springer, Heidelberg (2008). Scholar
  7. 7.
    Georgiou, C., Hadjistasi, T., Nicolaou, N., Schwarzmann, A.A.: Unleashing and speading up readers in atomic object implementations. (2018)
  8. 8.
    Hadjistasi, T., Nicolaou, N., Schwarzmann, A.A.: On the impossibility of one-and-a-half round atomic memory. (2016)
  9. 9.
    Hadjistasi, T., Nicolaou, N., Schwarzmann, A.A.: Oh-RAM! One and a half round atomic memory. In: El Abbadi, A., Garbinato, B. (eds.) NETYS 2017. LNCS, vol. 10299, pp. 117–132. Springer, Cham (2017). Scholar
  10. 10.
    Herlihy, M.P., Wing, J.M.: Linearizability: a correctness condition for concurrent objects. ACM Trans. Prog. Lang. Syst. 12(3), 463–492 (1990)CrossRefGoogle Scholar
  11. 11.
    Lamport, L.: How to make a multiprocessor computer that correctly executes multiprocess progranm. IEEE Trans. Comput. 28(9), 690–691 (1979)CrossRefGoogle Scholar
  12. 12.
    Lynch, N.: Distributed Algorithms. Morgan Kaufmann Publishers, Burlington (1996)zbMATHGoogle Scholar
  13. 13.
    Lynch, N.A., Shvartsman, A.A.: Robust emulation of shared memory using dynamic quorum-acknowledged broadcasts. In: Proceedings of FTCS 1997, pp. 272–281 (1997)Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Chryssis Georgiou
    • 1
  • Theophanis Hadjistasi
    • 2
    Email author
  • Nicolas Nicolaou
    • 3
    • 4
  • Alexander A. Schwarzmann
    • 2
  1. 1.Department of Computer ScienceUniversity of CyprusNicosiaCyprus
  2. 2.University of ConnecticutStorrsUSA
  3. 3.KIOS Research and Innovation Center of ExcellenceUniversity of CyprusNicosiaCyprus
  4. 4.Algolysis Ltd.NicosiaCyprus

Personalised recommendations