Fast Statistical Modelling of Temperature Variation on 28 nm FDSOI Technology

  • Abdelgader M. AbdallaEmail author
  • Isiaka A. Alimi
  • Manuel González
  • Issa Elfergani
  • Jonathan Rodriguez
Conference paper
Part of the Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering book series (LNICST, volume 263)


It is well known that the 28 nm fully depleted Silicon-On Insulator (FDSOI) node has a temperature effect due to the inherent pyroelectric and piezoelectric properties. In this paper, we introduce a spatial interpolation Lookup table (LUT) model considering temperature dependence of nanometer CMOS transistors. The novel methodology is used to build the bias current and capacitance LUTs for MOS transistor circuits under extensive variety of temperature values, evaluated under transient analysis. This innovative LUTs model significantly reduce the simulation runtime with sufficient accuracy using adaptive multivariate precomputed Barycentric relational interpolation for the appraisal temperature effects of 28 nm FDSOI node.

A transient analysis benchmark is employed in order to verify and validate the proposed models according to the well-known simulation models (i.e. the 28 nm FDSOI model and traditional spatial Lagrange model). The proposed model can significantly reduce the size of lookup table, thereby reducing the computational cost. Furthermore, the model outperform the 28 nm FDSOI compact physical model and the traditional spatial Lagrange model due to the reduced simulation runtime by up to eight orders of magnitude considering the temperature effect in 28 nm FDSOI innovation. Moreover, the proposed novel LUT based approaches are able to attain high precision with much reduced computational cost.


Statistical modelling Temperature variation 28 nm FDSOI technology 


  1. 1.
    Planes, N., et al.: 28nm FDSOI technology platform for high-speed low-voltage digital applications. In: VLSI Technology (VLSIT), 2012 Symposium, pp. 133–134. IEEE, Honolulu, HI (2012)Google Scholar
  2. 2.
    Salvatore, G.A., Lattanzio, L., Bouvet, D., Ionescu, A.M.: Modeling the temperature dependence of Fe-FET static characteristics based on Landau’s theory. IEEE Trans. Electron Devices 58(9), 3162–3169 (2011)CrossRefGoogle Scholar
  3. 3.
    Kumar, S.V., Kim, C.H., Sapatnekar, S.S.: Body bias voltage computations for process and temperature compensation. IEEE Trans. Very Large Scale Integr. VLSI Syst. 16(3), 249–262 (2008)CrossRefGoogle Scholar
  4. 4.
    Filanovsky, I.M., Allam, A.: Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits. IEEE Trans. Circ. Syst. I Fundam. Theor. Appl. 48(7), 876–884 (2001)CrossRefGoogle Scholar
  5. 5.
    Ku, J.C., Ismail, Y.: On the scaling of temperature-dependent effects. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 26(10), 1882–1888 (2007)CrossRefGoogle Scholar
  6. 6.
    Gildenblat, G., et al.: PSP: an advanced surface-potential-based MOSFET model for circuit simulation. IEEE Trans. Electron Devices 53(9), 1979–1993 (2006)CrossRefGoogle Scholar
  7. 7.
    Thakker, R.A., Sathe, C., Baghini, M.S., Patil, M.B.: A table-based approach to study the impact of process variations on FinFET circuit performance. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 29(4), 627–631 (2010)CrossRefGoogle Scholar
  8. 8.
    Bourenkov, V., McCarthy, K.G., Mathewson, A.: MOS table models for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 24(3), 352–362 (2005)CrossRefGoogle Scholar
  9. 9.
    Li, X., Yang, F., Wu, D., Zhou, Z., Zeng, X.: MOS table models for fast and accurate simulation of analog and mixed-signal circuits using efficient oscillation-diminishing interpolations. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 34(9), 1481–1494 (2015)CrossRefGoogle Scholar
  10. 10.
    Graham, M.G., Paulos, J.J.: Interpolation of MOSFET table data in width, length, and temperature. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 12(12), 1880–1884 (1993)CrossRefGoogle Scholar
  11. 11.
    Rofougaran, A., Abidi, A.A.: A table lookup FET model for accurate analog circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 12(2), 324–335 (1993)CrossRefGoogle Scholar
  12. 12.
    Schrom, G., Stach, A., Selberherr, A.S.: An interpolation based MOSFET model for low-voltage applications. Microelectron. J. 29(8), 529–534 (1998)CrossRefGoogle Scholar
  13. 13.
    Touhidur, R.: Physics Based Modeling of Multiple Gate Transistors on Silicon on-Insulator (SOI). The University of Tennessee, Knoxville (2009)Google Scholar
  14. 14.
    Abdalla, A.M., Elfergani, I.T.E., Rodriguez, J.: Modelling the temperature dependence of 28 nm Fully Depleted Silicon-On Insulator (FDSOI) static characteristics based on parallel computing approach. In: 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), pp. 1–2. IEEE, Toulouse (2016)Google Scholar
  15. 15.
    Hormann, K., Schaefer, S.: Pyramid algorithms for barycentric rational interpolation. Comput. Aided Geom. D. 42, 1–6 (2016)MathSciNetCrossRefGoogle Scholar
  16. 16.
    Berrut, J.P., Trefethen, L.N.: Barycentric lagrange interpolation. SIAM Rev. 46, 501–517 (2004)MathSciNetCrossRefGoogle Scholar
  17. 17.
    Zhao, A., Wang, B.: Lebesgue constant minimizing bivariate barycentric rational interpolation. Int. J. App. Maths Info. Sci 8(1), 187–192 (2014)MathSciNetCrossRefGoogle Scholar
  18. 18.
    Adams, B.M., et al.: DAKOTA, A Multilevel Parallel Object-Oriented Framework for Design Optimization, Parameter Estimation, Uncertainty Quantification, Technical report SAND2014-4253, Sandia National Laboratory (2014)Google Scholar
  19. 19.
    Goldman, R.: Pyramid algorithms A dynamic programming approach to curves and surfaces for Geometric Modeling. Morgan Kaufmann, San Francisco (2003)Google Scholar
  20. 20.
    Kilchytska, V., Makovejev, S., Md Arshad, M.K., Raskin, J.-P., Flandre, D.: Perspectives of UTBB FD SOI MOSFETs for analog and RF applications. In: Nazarov, A., Balestra, F., Kilchytska, V., Flandre, D. (eds.) Functional Nanomaterials and Devices for Electronics, Sensors and Energy Harvesting. EM, pp. 27–46. Springer, Cham (2014). Scholar
  21. 21.
    Snider, A.D.: Charge conservation and the transcapacitance element: an exposition. IEEE Trans. Educ. 38(4), 376–379 (1995)CrossRefGoogle Scholar
  22. 22.
    Lai, S., Fager, C., Kuylenstierna, D., Angelov, A.I.: LDMOS modeling. IEEE Microwave Mag. 14(1), 108–116 (2013)CrossRefGoogle Scholar
  23. 23.
    Jang, J.: Small-signal modeling of RF CMOS. Maters thesis, Dept. Elect. Eng; Stanford Univ.; Stanford, CA, USA (2004)Google Scholar
  24. 24.
    Chen, M., Zhao, W., Liu, F., Cao, Y.: Fast statistical circuit analysis with finite-point based transistor model. In: 2007 Design, Automation Test in Europe Conference Exhibition, Nice, pp. 1–6 (2007)Google Scholar

Copyright information

© ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering 2019

Authors and Affiliations

  • Abdelgader M. Abdalla
    • 1
    Email author
  • Isiaka A. Alimi
    • 1
  • Manuel González
    • 2
  • Issa Elfergani
    • 1
  • Jonathan Rodriguez
    • 1
  1. 1.Instituto de Telecomunicações, Department of Electronics, Telecommunications and Informatics (DETI)Universidade de AveiroAveiroPortugal
  2. 2.Evotel Informatica SLMadridSpain

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