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Efficient Process Variation Characterization by Virtual Probe

  • Jun TaoEmail author
  • Wangyang Zhang
  • Xin LiEmail author
  • Frank Liu
  • Emrah Acar
  • Rob A. Rutenbar
  • Ronald D. Blanton
  • Xuan ZengEmail author
Chapter

Abstract

In this chapter, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize, and monitor spatially correlated inter-die and/or intra-die variations in nanoscale manufacturing process. VP exploits recent breakthroughs in compressed sensing to accurately predict spatial variations from an exceptionally small set of measurement data, thereby reducing the cost of silicon characterization. By exploring the underlying sparse pattern in spatial frequency domain, VP achieves substantially lower sampling frequency than the well-known Nyquist rate. In addition, VP is formulated as a linear programming problem and, therefore, can be solved both robustly and efficiently. Our industrial measurement data demonstrate the superior accuracy of VP over several traditional methods including two-dimensional interpolation, Kriging prediction, and k-LSE estimation.

References

  1. 1.
    S. Nassif, Delay variability: sources, impacts and trends, in IEEE International Solid-State Circuits Conference (2000), pp. 368–369Google Scholar
  2. 2.
    Semiconductor Industry Associate, 2007 International Technology Roadmap for Semiconductors (ITRS) (Semiconductor Industry Association, Washington, 2007)Google Scholar
  3. 3.
    H. Chang, S. Sapatnekar, Statistical timing analysis under spatial correlations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), 1467–1482 (2005)CrossRefGoogle Scholar
  4. 4.
    C. Visweswariah, K. Ravindran, K. Kalafala, S. Walker, S. Narayan, First-order incremental block-based statistical timing analysis, in Design Automation Conference (2004), pp. 331–336Google Scholar
  5. 5.
    Y. Zhan, A. Strojwas, X. Li, L. Pileggi, D. Newmark, M. Sharma, Correlation aware statistical timing analysis with non-Gaussian delay distributions, in Design Automation Conference (2005), pp. 77–82Google Scholar
  6. 6.
    K. Heloue, F. Najm, Statistical timing analysis with two-sided constraints, in International Conference on Computer-Aided Design (2005), pp. 829–836Google Scholar
  7. 7.
    M. Mani, A. Singh, M. Orshansky, Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization, in International Conference on Computer-Aided Design (2006), pp. 19–26Google Scholar
  8. 8.
    S. Kulkarni, D. Sylvester, D. Blaauw, A statistical framework for post-silicon tuning through body bias clustering, in International Conference on Computer-Aided Design (2006), pp. 39–46Google Scholar
  9. 9.
    Q. Liu, S. Sapatnekar, Synthesizing a representative critical path for post-silicon delay prediction, in IEEE International Symposium on Physical Design (2009), pp. 183–190Google Scholar
  10. 10.
    M. Ketchen, M. Bhushan, D. Pearson, High speed test structures for in-line process monitoring and model calibration, in IEEE International Conference on Microelectronic Test Structures (2005), pp. 33–38Google Scholar
  11. 11.
    M. Bhushan, A. Gattiker, M. Ketchen, K. Das, Ring oscillators for CMOS process tuning and variability control. IEEE Trans. Semicond. Manuf. 19(1), 10–18 (2006)CrossRefGoogle Scholar
  12. 12.
    W. Mann, F. Taber, P. Seitzer, J. Broz, The leading edge of production wafer probe test technology, in IEEE International Test Conference (2004), pp. 1168–1195Google Scholar
  13. 13.
    F. Koushanfar, P. Boufounos, D. Shamsi, Post-silicon timing characterization by compressed sensing, in International Conference on Computer-Aided Design (2008), pp. 185–189Google Scholar
  14. 14.
    S. Reda, S. Nassif, Analyzing the impact of process variations on parametric measurements: novel models and applications, in Design, Automation & Test in Europe (2009), pp. 375–380Google Scholar
  15. 15.
    M. Bushnell, V. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits (Kluwer Academic Publishers, Norwell, 2000)Google Scholar
  16. 16.
    A. Oppenheim, Signals and Systems (Prentice Hall, Upper Saddle River, 1996)Google Scholar
  17. 17.
    R. Gonzalez, R. Woods, Digital Image Processing (Prentice Hall, Upper Saddle River, 2007)Google Scholar
  18. 18.
    D. Donoho, Compressed sensing. IEEE Trans. Inf. Theory 52(4), 1289–1306 (2006)MathSciNetCrossRefGoogle Scholar
  19. 19.
    E. Candes, Compressive sampling, in International Congress of Mathematicians (2006)Google Scholar
  20. 20.
    J. Tropp, S. Wright, Computational methods for sparse solution of linear inverse problems. Proc. IEEE 98(6), 948–958 (2010)CrossRefGoogle Scholar
  21. 21.
    D. Donoho, J. Tanner, Precise undersampling theorems. Proc. IEEE 98(6), 913–924 (2010)CrossRefGoogle Scholar
  22. 22.
    C. Bishop, Pattern Recognition and Machine Learning (Prentice Hall, Upper Saddle River, 2007)Google Scholar
  23. 23.
    W. Press, S. Teukolsky, W. Vetterling, B. Flannery, Numerical Recipes: The Art of Scientific Computing (Cambridge University Press, Cambridge, 2007)zbMATHGoogle Scholar
  24. 24.
    F. Liu, A general framework for spatial correlation modeling in VLSI design, in Design Automation Conference (2007), pp. 817–822Google Scholar
  25. 25.
    A. Nowroz, R. Cochran, S. Reda, Thermal monitoring of real processors: techniques for sensor allocation and full characterization, in Design Automation Conference (2010), pp. 56–61Google Scholar
  26. 26.
    R. Tibshirani, Regression shrinkage and selection via the Lasso. J. R. Stat. Soc. 58(1), 267–288 (1996)MathSciNetzbMATHGoogle Scholar
  27. 27.
    G. Golub, C. Loan, Matrix Computations (Johns Hopkins University Press, Baltimore, 1996)zbMATHGoogle Scholar
  28. 28.
    S. Boyd, L. Vandenberghe, Convex Optimization (Cambridge University Press, Cambridge, 2004)CrossRefGoogle Scholar
  29. 29.
    S. Kim, K. Koh, M. Lustig, S. Boyd, D. Gorinevsky, An interior-point method for large-scale l 1-regularized least squares. IEEE J. Sel. Top. Sign. Proces. 1(4), 606–617 (2007)CrossRefGoogle Scholar
  30. 30.
    M. McKay, R. Beckman, W. Conover, A comparison of three methods for selecting values of input variables in the analysis of output from computer code. Technometrics 42(1), 55–61 (1979)MathSciNetCrossRefGoogle Scholar
  31. 31.
    X. Li, R. Rutenbar, R. Blanton, Virtual probe: a statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits, in International Conference on Computer-Aided Design (2009), pp. 433–440Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.State Key Laboratory of ASIC and System, School of MicroelectronicsFudan UniversityShanghaiChina
  2. 2.Cadence Design Systems, Inc.PittsburghUSA
  3. 3.Department of Electrical and Computer EngineeringDuke UniversityDurhamUSA
  4. 4.IBM Research LaboratoryAustinUSA
  5. 5.IBM T. J. Watson Research CenterYorktown HeightsUSA
  6. 6.Department of Computer ScienceUniversity of Illinois at Urbana-ChampaignUrbanaUSA
  7. 7.Department of Electrical and Computer EngineeringCarnegie Mellon UniversityPittsburghUSA

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