Machine Learning Approaches for IC Manufacturing Yield Enhancement
Modern semiconductor manufacturing is highly automated and generates a large amount of data with every wafer and process step. There is an increasing interest in machine learning and data mining techniques to improve yield to take advantage of this increasing volume of data. In this chapter, we introduce machine learning yield models for integrated circuit (IC) manufacturing yield enhancement. Challenges in this area include class imbalance due to high manufacturing yield, and concept drift due to the time-varying environment. We present batch and online learning methods to tackle the imbalanced classification problem, and incremental machine learning frameworks to overcome concept drift. We consider the packaging and testing process in chip stack flash memory manufacturing as an application. By testing our methods on real data from industry, we show the possibility of packaged memory yield improvement with machine learning-based classifiers detecting bad dies before packaging. Experimental results show significant yield improvement potential. In a time-invariant environment, for stacks of eight dies, we can achieve an approximately 9% yield improvement. In a longer period of time with realistic concept drift, a naive approach using a fixed false alarm rate-based decision boundary is shown to fail to improve yield. In contrast, with optimal thresholds, our incremental learning approach achieves approximately 1.4% yield improvement in the eight-die stack case and 3.4% in the 16-die stack case.
We thank SanDisk Semiconductor (Shanghai) Co. Ltd. (SDSS) for assistance and support. We also thank Professor Roy Welsch from MIT Sloan School of Management, and Honghong Chen, Fangfang You, Wenting Zhang, and Yew Wee Cheong from SDSS for helpful discussions.
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