Extreme Statistics in Memories
Memory design specifications typically include yield requirements, apart from performance and power requirements. These yield requirements are usually specified for the entire memory array at some supply voltage and temperature conditions. For example, the designer may be comfortable with an array failure probability of one in a thousand at 100∘C and 1 V supply, i.e., Ff,array ≤ 10−3. However, how does this translate to a yield requirement for the memory cell? How do we even estimate the statistical distribution of memory cell performance metrics in this extreme rare event regime? We will answer these questions and in the process see the application of certain machine learning techniques and extreme value theory in memory design.
This work was supported by the MARCO/DARPA Focus Research Center for Circuit and System Solutions (C2S2) and the Semiconductor Research Corporation.
- 9.J.R.M. Hosking, The theory of probability weighted moments, IBM Research Report, RC12210, 1986Google Scholar
- 10.T. Joachims, Making large-scale SVM learning practical, in Advances in Kernel Methods - Support Vector Learning, ed. by B. Schölkopf, C. Burges, A. Smola (MIT Press, Cambridge, 1999)Google Scholar
- 11.B. Joshi, R.K. Anand, C. Berg, J. Cruz-Rios, A. Krishnamurthi, N. Nettleton, S. Ngu-yen, J. Reaves, J. Reed, A. Rogers, S. Rusu, C. Tucker, C. Wang, M. Wong, D. Yee, J.-H. Chang, A BiCMOS 50MHz cache controller for a superscalar microprocessor, in International Solid-State Circuits Conference (1992)Google Scholar
- 12.R.K. Krishnamurthy, A. Alvandpour, V. De, S. Borkar, High-performance and low-power challenges for sub-70nm microprocessor circuits, in Proceedings of Custom Integrated Circuits Conference (2002)Google Scholar
- 13.W. Liu, X. Jin, J. Chen, M.-C. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P. Ko, C. Hu, BSIM 3v3.2 Mosfet Model Users’ Manual, Tech. Report No. UCB/ERL M98/51, University of California, Berkeley, 1988Google Scholar
- 14.K. Morik, P. Brockhausen, T. Joachims, Combining statistical learning with a knowledge-based approach - a case study in intensive care monitoring, in Proceedings of 16th International Conference on Machine Learning (1999)Google Scholar
- 18.A. Singhee, Novel algorithms for fast statistical analysis of scaled circuits. PhD Thesis, Electrical and Computer Engineering, Carnegie Mellon University (2007)Google Scholar
- 19.A. Singhee, SiLVR: projection pursuit for response surface modeling, in Machine Learning in VLSI Computer Aided Design, ed. by I.M. Elfadel, D. Boning, X. Li (Springer, Berlin, 2018)Google Scholar
- 20.A. Singhee, R.A. Rutenbar, Statistical Blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application, in Proceedings of Design Automation & Test in Europe (2007)Google Scholar
- 21.A. Singhee, R.A. Rutenbar, Beyond low-order statistical response surfaces: latent variable regression for efficient, highly nonlinear fitting, in Proceedings of IEEE/ACM Design Automation Conference (2007)Google Scholar
- 23.A. Singhee, J. Wang, B.H. Calhoun, R.A. Rutenbar, Recursive Statistical Blockade: an enhanced technique for rare event simulation with application to SRAM circuit design, in Proceeding of International Conference on VLSI Design (2008)Google Scholar
- 26.J. Wang, A. Singhee, R.A. Rutenbar, B.H. Calhoun, Modeling the minimum standby supply voltage of a full SRAM array, in Proceedings of European Solid-State Circuits Conference (2007)Google Scholar