Advertisement

Modeling Counters

  • Brock J. LaMeres
Chapter

Abstract

Counters are a special case of finite state machines because they move linearly through their discrete states (either forward or backward) and typically are implemented with state-encoded outputs. Due to this simplified structure and widespread use in digital systems, VHDL allows counters to be modeled using a single process and with arithmetic operators (i.e., + and −). This enables a more compact model and allows much wider counters to be implemented. This chapter will cover some of the most common techniques for modeling counters.

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Brock J. LaMeres
    • 1
  1. 1.Department of Electrical & Computer EngineeringMontana State UniversityBozemanUSA

Personalised recommendations