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General Overview of the Basic Structure and Operation of a Typical Silicon on Insulator Metal–Semiconductor Field Effect Transistor (SOI-MESFET)

  • Iraj Sadegh Amiri
  • Hossein Mohammadi
  • Mahdiar Hosseinghadiry
Chapter

Abstract

This chapter states the physics and fundamental concepts related to different types of field effect transistors. The necessities and various strategies related to scaling are explained. A detailed description of the origin and impact of various short-channel effects associated with downscaling and their influence on the normal operation of MOS transistors are described. The different technical solutions presented to resolve the problems caused by short-channel effects are discussed. Finally, the structures and advantages of non-classical devices and their feasibility in the settling of the short-channel effects are described.

Keywords

Physics and fundamental concepts Field effect transistors MOS transistors 

References

  1. 1.
    K. Gupta, N. Gupta, Advanced Semiconducting Materials and Devices (Springer, Berlin, 2016)CrossRefGoogle Scholar
  2. 2.
    J.B. Kuo, K.-W. Su, CMOS VLSI Engineering: Silicon-on-Insulator (SOI) (Springer, Berlin, 2013)Google Scholar
  3. 3.
    I. Bahl, Fundamentals of RF and Microwave Transistor Amplifiers (Wiley, Hoboken, 2009)CrossRefGoogle Scholar
  4. 4.
    L.I. Berger, Semiconductor Materials (CRC Press, Boca Raton, 1996)Google Scholar
  5. 5.
    M. Golio, RF and Microwave Semiconductor Device Handbook (CRC Press, Boca Raton, 2017)Google Scholar
  6. 6.
    S. Henzler, Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies (Springer, Berlin, 2006)Google Scholar
  7. 7.
    S. Saurabh, M.J. Kumar, Fundamentals of Tunnel Field-Effect Transistors (CRC Press, Boca Raton, 2016)CrossRefGoogle Scholar
  8. 8.
    S.M. Kang, Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design (TMH, New Delhi, 2003)Google Scholar
  9. 9.
    F. D’Agostino, D. Quercia, Short-channel effects in MOSFETs, 2000. Accessed online http://www0.cs.ucl.ac.uk/staff/d.quercia/projects/vlsi/report.pdf
  10. 10.
    A.K. Singh, Electronic Devices and Integrated Circuits (PHI Learning Pvt. Ltd., New Delhi, 2011)Google Scholar
  11. 11.
    L. Wang, Quantum Mechanical Effects on MOSFET Scaling Limit (Citeseer, 2006)Google Scholar
  12. 12.
    L. Wilson, International Technology Roadmap for Semiconductors (ITRS) (Semiconductor Industry Association, Washington, 2013)Google Scholar
  13. 13.
    T. Skotnicki, J.A. Hutchby, T.-J. King, H.-S. Wong, F. Boeuf, The end of CMOS scaling: Toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits Devices Mag. 21, 16–26 (2005)CrossRefGoogle Scholar
  14. 14.
    L. Hyunjin, L. Jongho, S. Hyungcheol, DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate nonoverlapped structure. IEEE Trans. Nanotechnol. 1, 219–225 (2002)CrossRefGoogle Scholar
  15. 15.
    G.G. Shahidi, in 2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings of Technical Papers. SOI Technology for the GHz Era (IEEE, 2001), pp. 11–14Google Scholar
  16. 16.
    P. Feng, Design, Modeling and Analysis of Non-classical Field Effect Transistors, 2012Google Scholar
  17. 17.
    A. Kranti, S. Haldar, R. Gupta, Analytical model for threshold voltage and I–V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET. Microelectron. Eng. 56, 241–259 (2001)CrossRefGoogle Scholar
  18. 18.
    W. Ma, Linearity Analysis of Single and Double-Gate Silicon-On-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistor (Ohio University, Athens, 2004)Google Scholar
  19. 19.
    S. Shee, Quantum Analytical Modeling of Ultrathin DMDG SON MOSFET: A Performance Assessment (Jadavpur University, Kolkata, 2014)Google Scholar
  20. 20.
    J.B. Kuo, S.-C. Lin, Low-Voltage SOI CMOS VLSI Devices and Circuits (Wiley, Hoboken, 2004)Google Scholar
  21. 21.
    S. Crisoloveanu, S. Li, Electrical Characterization of SOI Materials and Devices (Kluwer Academic Publishers, Dordrecht, 1995)Google Scholar
  22. 22.
    P. Jong-Tae, J.P. Colinge, Multiple-gate SOI MOSFETs: device design guidelines. IEEE Trans. Electron Devices 49, 2222–2229 (2002)CrossRefGoogle Scholar
  23. 23.
    T. Sekigawa, Y. Hayashi, Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate. Solid State Electron. 27, 827–828 (1984)CrossRefGoogle Scholar
  24. 24.
    L. Hyung-Kyu, J.G. Fossum, Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's. IEEE Trans. Electron Devices 30, 1244–1251 (1983)CrossRefGoogle Scholar
  25. 25.
    C. Mallikarjun, K.N. Bhat, Numerical and charge sheet models for thin-film SOI MOSFETs. IEEE Trans. Electron Devices 37, 2039–2051 (1990)CrossRefGoogle Scholar
  26. 26.
    J.-T. Park, J.-P. Colinge, C.H. Diaz, Pi-gate SOI MOSFET. IEEE Electron Device Lett. 22, 405–406 (2001)CrossRefGoogle Scholar
  27. 27.
    H.-W. Gao, T.K. Chiang, in 2013 IEEE 10th International Conference on ASIC (ASICON). A Novel Scaling Theory For Fully-depleted Omega-gate (ΩG) MOSFETs (IEEE, 2013), pp. 1–3Google Scholar
  28. 28.
    S. Jae Young, C. Woo Young, P.J. Hee, L. Jong Duk, P. Byung-Gook, Design optimization of gate-all-around (GAA) MOSFETs. IEEE Trans. Nanotechnol. 5, 186–191 (2006)CrossRefGoogle Scholar
  29. 29.
    B. Yang, K.D. Buddharaju, S.H.G. Teo, N. Singh, G.Q. Lo, D.L. Kwong, Vertical silicon-nanowire formation and gate-all-around MOSFET. IEEE Electron Device Lett. 29, 791–794 (2008)CrossRefGoogle Scholar
  30. 30.
    F. Schwierz, J.J. Liou, H. Wong, Nanometer CMOS (Pan Stanford, 2010)Google Scholar
  31. 31.
    G. Hellings, K. De Meyer, High Mobility and Quantum Well Transistors (Springer, Berlin, 2013)CrossRefGoogle Scholar
  32. 32.
    R. Ismail, M.T. Ahmadi, S. Anwar, Advanced Nanoelectronics (CRC Press, Boca Raton, 2012)Google Scholar
  33. 33.
    A. Chaudhry, J. Roy, G. Joshi, Nanoscale strained-Si MOSFET physics and modeling approaches: A review. J. Semicond. 31, 104001 (2010)CrossRefGoogle Scholar
  34. 34.
    D. Yuehua, H. Yuan, Q. Liu, K. Daoming, C. Junning, in IEEE Asia Pacific Conference on Circuits and Systems, 2006. APCCAS 2006. Physics-based Modeling and Simulation of Dual Material Gate (DMG) LDMOS (IEEE, 2006), pp. 1500–1503Google Scholar
  35. 35.
    M.J. Kumar, A. Chaudhry, Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs. IEEE Trans. Electron Devices 51, 569–574 (2004)CrossRefGoogle Scholar
  36. 36.
    C.W. Mueller, P.H. Robinson, Grown-film silicon transistors on sapphire. Proc. IEEE 52, 1487–1490 (1964)CrossRefGoogle Scholar
  37. 37.
    T. Toyabe, S. Asai, Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's derived from two-dimensional analysis. IEEE Trans. Electron Devices 26, 453–461 (1979)CrossRefGoogle Scholar
  38. 38.
    E. Sano, R. Kasai, K. Ohwada, H. Ariyoshi, A two-dimensional analysis for MOSFET's fabricated on buried SiO2 layer. IEEE Trans. Electron Devices 27, 2043–2050 (1980)CrossRefGoogle Scholar
  39. 39.
    E.R. Worley, Theory of the fully depleted SOS/MOS transistor. Solid State Electron. 23, 1107–1111 (1980)CrossRefGoogle Scholar
  40. 40.
    Y. Omura, A simple model for short-channel effects of a buried-channel MOSFET on the buried insulator. IEEE Trans. Electron Devices 29, 1749–1755 (1982)CrossRefGoogle Scholar
  41. 41.
    L. Hyung-Kyu, J.G. Fossum, Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's. IEEE Trans. Electron Devices 30, 1244–1251 (1983)CrossRefGoogle Scholar
  42. 42.
    L. Hyung-Kyu, J.G. Fossum, Current-voltage characteristics of thin-film SOI MOSFET’s in strong inversion. IEEE Trans. Electron Devices 31, 401–408 (1984)CrossRefGoogle Scholar
  43. 43.
    J.P. Colinge, Subthreshold slope of thin-film SOI MOSFET's. IEEE Electron Device Lett. 7, 244–246 (1986)CrossRefGoogle Scholar
  44. 44.
    F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, T. Elewa, Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance. IEEE Electron Device Lett. 8, 410–412 (1987)CrossRefGoogle Scholar
  45. 45.
    K.K. Young, Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans. Electron Devices 36, 399–402 (1989)CrossRefGoogle Scholar
  46. 46.
    S. Veeraraghavan, J.G. Fossum, Short-channel effects in SOI MOSFETs. IEEE Trans. Electron Devices 36, 522–528 (1989)CrossRefGoogle Scholar
  47. 47.
    H.T. Chen, R.S. Huang, An analytical model for back-gate effects on ultrathin-film SOI MOSFETs. IEEE Electron Device Lett. 12, 433–435 (1991)CrossRefGoogle Scholar
  48. 48.
    R.H. Yan, A. Ourmazd, K.F. Lee, Scaling the Si MOSFET: From bulk to SOI to bulk. IEEE Trans. Electron Devices 39, 1704–1710 (1992)CrossRefGoogle Scholar
  49. 49.
    K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, Y. Arimoto, Scaling theory for double-gate SOI MOSFET’s. IEEE Trans. Electron Devices 40, 2326–2329 (1993)CrossRefGoogle Scholar
  50. 50.
    P. Francis, A. Terao, D. Flandre, F. Van de Wiele, Modeling of ultrathin double-gate nMOS/SOI transistors. IEEE Trans. Electron Devices 41, 715–720 (1994)CrossRefGoogle Scholar
  51. 51.
    Y. Tosaka, K. Suzuki, T. Sugii, Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET’s. IEEE Electron Device Lett. 15, 466–468 (1994)CrossRefGoogle Scholar
  52. 52.
    K. Suzuki, T. Sugii, Analytical models for n +-p+ double-gate SOI MOSFET’s. IEEE Trans. Electron Devices 42, 1940–1948 (1995)CrossRefGoogle Scholar
  53. 53.
    S.R. Banna, M. Chan, P.K. Ko, C.T. Nguyen, C. Mansun, Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET’s. IEEE Trans. Electron Devices 42, 1949–1955 (1995)CrossRefGoogle Scholar
  54. 54.
    W. Long, H. Ou, J.M. Kuo, K.K. Chin, Dual-material gate (DMG) field effect transistor. IEEE Trans. Electron Devices 46, 865–870 (1999)CrossRefGoogle Scholar
  55. 55.
    K. Suzuki, S. Pidin, Short-channel single-gate SOI MOSFET model. IEEE Trans. Electron Devices 50, 1297–1305 (2003)CrossRefGoogle Scholar
  56. 56.
    A. Chaudhry, M.J. Kumar, Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: A review. IEEE Trans. Device Mater. Reliab. 4, 99–109 (2004)CrossRefGoogle Scholar
  57. 57.
    A. Chaudhry, M.J. Kumar, Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET. IEEE Trans. Electron Devices 51, 1463–1467 (2004)CrossRefGoogle Scholar
  58. 58.
    W. Ma, S. Kaya, Impact of device physics on DG and SOI MOSFET linearity. Solid State Electron. 48, 1741–1746 (2004)CrossRefGoogle Scholar
  59. 59.
    J.-P. Colinge, Multiple-gate SOI MOSFETs. Solid State Electron. 48, 897–905 (2004)CrossRefGoogle Scholar
  60. 60.
    G.V. Reddy, M.J. Kumar, A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation. IEEE Trans. Nanotechnol. 4, 260–268 (2005)CrossRefGoogle Scholar
  61. 61.
    S. Baishya, A. Mallik, C.K. Sarkar, A pseudo two-dimensional subthreshold surface potential model for dual-material gate MOSFETs. IEEE Trans. Electron Devices 54, 2520–2525 (2007)CrossRefGoogle Scholar
  62. 62.
    H.A.E. Hamid, J.R. Guitart, B. Iniguez, Two-dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double-gate MOSFETs. IEEE Trans. Electron Devices 54, 1402–1408 (2007)CrossRefGoogle Scholar
  63. 63.
    W. Yang, Y. Zhiping, T. Lilin, Scaling theory for FinFETs based on 3-D effects investigation. IEEE Trans. Electron Devices 54, 1140–1147 (2007)CrossRefGoogle Scholar
  64. 64.
    P. Agarwal, G. Saraswat, M.J. Kumar, Compact surface potential model for FD SOI MOSFET considering substrate depletion region. IEEE Trans. Electron Devices 55, 789–795 (2008)CrossRefGoogle Scholar
  65. 65.
    T.-K. Chiang, A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFET’s. Microelectron. Reliab. 49, 113–119 (2009)CrossRefGoogle Scholar
  66. 66.
    S. Jooyoung, Y. Bo, Y. Yu, T. Yuan, A review on compact modeling of multiple-gate MOSFETs. IEEE Trans. Circuits Syst. I Regul. Pap. 56, 1858–1869 (2009)MathSciNetCrossRefGoogle Scholar
  67. 67.
    R. Ritzenthaler, F. Lime, O. Faynot, S. Cristoloveanu, B. Iñiguez, 3D analytical modelling of subthreshold characteristics in vertical multiple-gate FinFET transistors. Solid State Electron. 65–66, 94–102 (2011)CrossRefGoogle Scholar
  68. 68.
    K. Meel, R. Gopal, D. Bhatnagar, Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s. Solid State Electron. 62, 174–184 (2011)CrossRefGoogle Scholar
  69. 69.
    A. Tsormpatzoglou, D.H. Tassis, C.A. Dimitriadis, G. Ghibaudo, N. Collaert, G. Pananakakis, Analytical threshold voltage model for lightly doped short-channel tri-gate MOSFETs. Solid State Electron. 57, 31–34 (2011)CrossRefGoogle Scholar
  70. 70.
    A. Kloes, M. Schwarz, T. Holtij, MOS3: A new physics-based explicit compact model for lightly doped short-channel triple-gate SOI MOSFETs. IEEE Trans. Electron Devices 59, 349–358 (2012)CrossRefGoogle Scholar
  71. 71.
    P. Vimala, N.B. Balamurugan, New analytical model for nanoscale tri-gate SOI MOSFETs including quantum effects. IEEE J. Electron Devices Soc. 2, 1–7 (2014)CrossRefGoogle Scholar
  72. 72.
    S. Tripathi, V. Narendar, A three-dimensional (3D) analytical model for subthreshold characteristics of uniformly doped FinFET. Superlattice. Microst. 83, 476–487 (2015)CrossRefGoogle Scholar
  73. 73.
    J.D. Marshall, J.D. Meindl, An analytical two-dimensional model for silicon MESFETs. IEEE Trans. Electron Devices 35, 373–383 (1988)CrossRefGoogle Scholar
  74. 74.
    H. Chin-Shan, W. Ching-Yuan, A 2-D analytic model for the threshold-voltage of fully depleted short gate-length Si-SOI MESFETs. IEEE Trans. Electron Devices 42, 2156–2162 (1995)CrossRefGoogle Scholar
  75. 75.
    J.G. Cao, A simplified 2-D analytic model for the threshold-voltage of fully depleted short gate-length Si-SOI MESFET’s. IEEE Trans. Electron Devices 43, 1314–1315 (1996)CrossRefGoogle Scholar
  76. 76.
    T.K. Chiang, Y.H. Wang, M.P. Houng, Modeling of threshold voltage and subthreshold swing of short-channel SOI MESFET’s. Solid State Electron. 43, 123–129 (1999)CrossRefGoogle Scholar
  77. 77.
    P. Pandey, B.B. Pal, S. Jit, A new 2-D model for the potential distribution and threshold voltage of fully depleted short-channel Si-SOI MESFETs. IEEE Trans. Electron Devices 51, 246–254 (2004)CrossRefGoogle Scholar
  78. 78.
    S. Jit, P. Pandey, A. Kumar, S.K. Gupta, Modified boundary condition at Si–SiO2 interface for modeling of threshold voltage and subthreshold swing of short-channel SOI MESFET’s. Solid State Electron. 49, 141–143 (2005)CrossRefGoogle Scholar
  79. 79.
    S. Jit, P.K. Pandey, P.K. Tiwari, Modeling of the subthreshold current and subthreshold swing of fully depleted short-channel Si–SOI-MESFETs. Solid State Electron. 53, 57–62 (2009)CrossRefGoogle Scholar
  80. 80.
    C.H. Suh, Analytical model for deriving the threshold voltage of a short gate SOI MESFET with vertically non-uniformly doped silicon film. Circuits Devices Syst. IET 4, 525–530 (2010)CrossRefGoogle Scholar
  81. 81.
    P. Hashemi, A. Behnam, E. Fathi, A. Afzali-Kusha, M. El Nokali, 2-D modeling of potential distribution and threshold voltage of short channel fully depleted dual material gate SOI MESFET. Solid State Electron. 49, 1341–1346 (2005)CrossRefGoogle Scholar
  82. 82.
    T.K. Chiang, in 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. The New Analytical Subthreshold Behavior Model For Dual Material Gate (DMG) SOI MESFET (2008), pp. 288–289Google Scholar
  83. 83.
    N. Lakhdar, F. Djeffal, A two-dimensional analytical model of subthreshold behavior to study the scaling capability of deep submicron double-gate GaN-MESFETs. J. Comput. Electron. 10, 382–387 (2011)CrossRefGoogle Scholar
  84. 84.
    A.A. Orouji, Z. Ramezani, S.M. Sheikholeslami, A novel SOI-MESFET structure with double protruded region for RF and high voltage applications. Mater. Sci. Semicond. Process. 30, 545–553 (2015)CrossRefGoogle Scholar

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© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Iraj Sadegh Amiri
    • 1
    • 2
  • Hossein Mohammadi
    • 3
  • Mahdiar Hosseinghadiry
    • 4
  1. 1.Computational Optics Research Group, Advanced Institute of Materials ScienceTon Duc Thang UniversityHo Chi Minh CityVietnam
  2. 2.Faculty of Applied SciencesTon Duc Thang UniversityHo Chi Minh CityVietnam
  3. 3.Pasargad Higher Education InstituteShirazIran
  4. 4.Allseas EngineeringDELFTThe Netherlands

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