Modified Low-Power Built-in Self-test for Image Processing Application

  • P. AnithaEmail author
  • P. Ramanathan
  • P. T. Vanathi
Conference paper
Part of the Lecture Notes in Computational Vision and Biomechanics book series (LNCVB, volume 31)


In recent trend, optimization of power without degradation of performance is major concern in application areas like embedded systems digital image and signal processing. The proper selection of test pattern/test image is one of the major issues. Our motivation of this work is to reduce the total power dissipation and area overhead of a Test pattern generator. The proposed BIST uses Negative Edge triggered D-Flip flop (NEDFF) for random pattern generation. When compared to existing LFSR with regular D-FF, our Modified LFSR with NEDFF reduces the count of transistors extensively. BIST using NEDFF is implemented and simulated using Microwind tool with 90 nm technology. The result reveals that significant amount of total power consumption is reduced while testing a VLSI circuit with NEDFF.


Low-power testing Less area NEDFF Power consumption Switching activity Medical image processing 



We would like to thank the management and principal of Sri Krishna college of Engineering and Technology, Coimbatore for providing the necessary facilities and support.


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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Department of ECESri Krishna College of Engineering & TechnologyCoimbatoreIndia
  2. 2.Department of ECEMadanapalle Institute of Technology & ScienceAngalluIndia
  3. 3.Department of ECEPSG College of TechnologyCoimbatoreIndia

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