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R&D on Electronic Devices and Circuits for the HL-LHC

  • Alberto Stabile
  • Attilio Andreazza
  • Mauro Citterio
  • Luca Frontini
  • Valentino Liberali
  • Chiara Meroni
  • Jafar Shojaii
Conference paper

Abstract

The paper presents the research activities in microelectronics, aiming at improving detection capabilities of future High Energy Physics (HEP) experiments. The output of this research will be the development of novel integrated circuits, to enhance the performance of electronic systems for the High Luminosity Large Hadron Collider (HL-LHC). In particular, the main research activities are focused on monolithic pixel arrays, on new digital architectures for pixel readout in 65 nm CMOS, and on associative memories for several interdisciplinary applications, such as fast tracking for trigger, DNA sequencing, magnetic resonance and image analysis.

Keywords

HL-LHC Microelectronics Pixel detector Associative memory 

References

  1. 1.
    G. Aad et al., JINST 3, P07007 (2008).  https://doi.org/10.1088/1748-0221/3/07/P07007; CMS Collaboration, JINST 3, S08004 (2008).  https://doi.org/10.1088/1748-0221/3/08/S08004; LHCb collaboration, LHCb VELO upgrade technical design report, CERN-LHCC-2013-021, https://cds.cern.ch/record/1624070
  2. 2.
    G. Contin et al., JINST 10, C03026 (2015).  https://doi.org/10.1088/1748-0221/10/03/C03026; ALICE Collaboration, J. Phys. G 41, 087002 (2014).  https://doi.org/10.1088/0954-3899/41/8/087002; T. Behnke et al., International Linear Collider Technical Design Report—Volume 4: Detectors, arXiv:1306.6329
  3. 3.
    I. Peric, Nucl. Instr. Method A 582, 876 (2007).  https://doi.org/10.1016/j.nima.2007.07.108
  4. 4.
    R. Roggero et al., Proceedings of the 25th International Symposium on Power Semiconductor Devices and ICs (ISPSD2013), May 2013, pp. 361–364Google Scholar
  5. 5.
    A. Andreazza et al., JINST 11, C11038 (2016). https://doi.org/10.1088/1748-0221/11/11/C11038
  6. 6.
    I. Peric et al., JINST 12, C02030 (2017). https://doi.org/10.1088/1748-0221/12/02/C02030
  7. 7.
    N. Demaria et al., CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments, in Proceedings of the IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), June 2015. https://doi.org/10.1109/IWASI.2015.7184947
  8. 8.
    S. Shojaii et al., A radiation hardened static RAM for high-energy physics experiments, in Proceedings of the International Conference on Microelectronics (MIEL), May 2014. https://doi.org/10.1109/MIEL.2014.6842164
  9. 9.
    A. Andreani et al., The AMchip04 and the processing unit prototype for the FastTracker. IOP J. Instr. 7, C08007 (2012). https://doi.org/10.1088/1748-0221/7/08/C08007/
  10. 10.
    L. Frontini et al., A new XOR-based content addressable memory architecture, in Proceedings of the ICECS, Seville (2012), pp. 701–704. https://doi.org/10.1109/ICECS.2012.6463629

Copyright information

© Springer Nature Switzerland AG 2018

Authors and Affiliations

  • Alberto Stabile
    • 1
    • 2
  • Attilio Andreazza
    • 1
    • 2
  • Mauro Citterio
    • 2
  • Luca Frontini
    • 1
    • 2
  • Valentino Liberali
    • 1
    • 2
  • Chiara Meroni
    • 2
  • Jafar Shojaii
    • 2
    • 3
  1. 1.Dipartimento di Fisica “Aldo Pontremoli”Università degli Studi di MilanoMilanItaly
  2. 2.Istituto Nazionale di Fisica NucleareMilanItaly
  3. 3.The University of MelbourneParkvilleAustralia

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