Advertisement

Low-Power High-Speed Hybrid Multiplier Architectures for Image Processing Applications

  • U. SaravanakumarEmail author
  • P. Suresh
  • V. Karthikeyan
Conference paper
Part of the Lecture Notes in Computational Vision and Biomechanics book series (LNCVB, volume 30)

Abstract

Multipliers play an imperative role in communication, signal and image processing, and embedded ASICs. Generally, multipliers are designed through various steps and they are occupying more area in the hardware, consumes more power, and causes an effect on performance. This paper is aimed to implement low-area and high-speed multiplier using various data compressors in partial product stages and tested for image processing. To suppress the vertical dimension of the partial product stage in multiplier, Sklansky adder is considered for the last stage and five hybrid multiplier architectures (HyMUL1–HyMUL5) have been implemented. For application verification, the two grayscale images are given as the inputs of the proposed multipliers and produce a new image which is an overlap of the two input images. The comparative analysis indicates that the proposed multiplier HyMUL2 consumed less area compared to other multipliers and its speed is also improved. The obtained new overlapped image using proposed multiplier HyMUL2 has high PSNR and low NMED.

Keywords

Data compressors Low area High speed PSNR NMED 

References

  1. 1.
    Momeni JH, Montuschi P, Lombardi F (2014) Design and analysis of approximate compressors for multiplication. IEEE Trans Comput 64(4):984–994MathSciNetCrossRefGoogle Scholar
  2. 2.
    Han J, Orshansky M (2013) Approximate computing: an emerging paradigm for energy-efficient design. In: IEEE ETS, pp 1–6Google Scholar
  3. 3.
    Chang P, Ahmadi M (2009) High speed low power 4:2 compressor cell design. In: International symposium on signals, circuits and systems, Iasi, pp 1–4Google Scholar
  4. 4.
    Chang C, Gu J, Zhang M (2004) Ultra Low-voltage low- power CMOS 4-2 and 5-2 Compressors for fast arithmetic circuits. IEEE Trans Circuits Syst 51(10):1985–1997CrossRefGoogle Scholar
  5. 5.
    Gu J, Chang CH (2003) Ultra low-voltage, low-power 4-2 compressor for high speed multiplications. In: 36th IEEE international symposium circuits systems, Bangkok, ThailandGoogle Scholar
  6. 6.
    Margala M, Durdle NG (1999) Low-power low-voltage 4-2 compressors for VLSI applications. In: IEEE Alessandro volta memorial workshop low-power design, pp 84–90Google Scholar
  7. 7.
    Parhami B (2010) Computer arithmetic: algorithms and hardware designs, 2nd edn. Oxford University Press, New YorkGoogle Scholar
  8. 8.
    Prasad K, Parhi KK (2001) Low-power 4-2 and 5-2 compressors. In: 35th Asilomar conference on signals, systems and computers, vol 1, pp 129–133Google Scholar
  9. 9.
    Ercegovac MD, Tomas L (2003) Digital arithmetic. Elsevier, AmsterdamGoogle Scholar
  10. 10.
    Ma J, Man K, Krilavicius T, Guan S, Jeong T (2011) Implementation of high performance multipliers based on approximate compressor design. In: International conference on electrical and control technologies (ECT), pp 96–100Google Scholar
  11. 11.
    Mahdiani HR, Ahmadi A, Fakhraie SM, Lucas C (2010) Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. IEEE Trans Circ Syst I: Regul Pap 57(4):850–862MathSciNetGoogle Scholar
  12. 12.
    Schulte MJ, Swartzlander EE (1993) Truncated multiplication with correction constant. In: IEEE workshop on VLSI signal processing VI, pp 388–396Google Scholar
  13. 13.
    King EJ, Swartzlander EE (1998) Data dependent truncated scheme for parallel multiplication. In: 31st Asilomar conference on signals, circuits and systems, pp 1178–1182Google Scholar
  14. 14.
    Kulkarni P, Gupta P, Ercegovac MD (2011) Trading accuracy for power in a multiplier architecture. J Low Power Electron 7(4):490–501CrossRefGoogle Scholar
  15. 15.
    Kelly D, Phillips B, Al-Sarawi S (2009) Approximate signed binary integer multipliers for arithmetic data value speculation. In: Conference on design and architectures for signal and image processing, pp 97–104Google Scholar
  16. 16.
    Menon R, Rdhakrishnan D (2006) High performance 5:2 compressor architectures. In: IEE Proceeding of circuits devices systems, vol 153, no 5Google Scholar
  17. 17.
    Sankar DR, Ali SA (2013) Design of Wallace tree multiplier by Sklansky adder. Int J Eng Res Appl 3(1):1036–1040Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Department of ECEVel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and TechnologyChennaiIndia

Personalised recommendations