A Hyhpercube Design on WSI

  • H. Ito
  • N. Suzuki

Abstract

Many processor networks have been proposed for massively parallel processing and high speed pipeline processing1. The network connects many identical processing elements (PEs) into a regular array structure, and has a huge processing power. The hypercube network (HC) has been focussed as a general type high speed processing architecture since it has many advantages as follows. It can connect a great number of PEs to provide a high processing power, it has short average distance and many paths between two PEs, and it contains many types of subnetworks in itself such as ring, tree, grid, and so on. An international conference concerning HC has been held every year2 and commercial HC machines have appeared1.

Keywords

Processor Array Plane Layout Processor Network Connection Relation Hypercube Network 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • H. Ito
    • 1
  • N. Suzuki
    • 1
  1. 1.Dept. of Electrical and Electronics Engr.Chiba University1-33 Yayoi-cho, Chiba-shiJapan

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