A Hyhpercube Design on WSI

  • H. Ito
  • N. Suzuki


Many processor networks have been proposed for massively parallel processing and high speed pipeline processing1. The network connects many identical processing elements (PEs) into a regular array structure, and has a huge processing power. The hypercube network (HC) has been focussed as a general type high speed processing architecture since it has many advantages as follows. It can connect a great number of PEs to provide a high processing power, it has short average distance and many paths between two PEs, and it contains many types of subnetworks in itself such as ring, tree, grid, and so on. An international conference concerning HC has been held every year2 and commercial HC machines have appeared1.


Processor Array Plane Layout Processor Network Connection Relation Hypercube Network 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    D.A. Reed and R.M. Fujimoto: “Multicomputer Networks”, The MIT Press, 1987.Google Scholar
  2. 2.
    First. Second and Third International Conferences on Hypercube Multiprocessors, SIAM, 1986, 1987, 1988.Google Scholar
  3. 3.
    C. Jesshope and W. Moore (ed.): “Wafer Scale Integration”, Adam Hilger, 1986 (Proc. IFIP WG 10.5 Workshop on Wafer Scale Integration, Grenoble, 1986).Google Scholar
  4. 4.
    G. Saucier and J. Trilhe (ed.): “Wafer Scale Integration”, North-Holland, 1986 (Proc. Workshop on Wafer Scale Integration, Southampton, 1985).Google Scholar
  5. 5.
    K. Yamashita, A. Kanasugi, S. Tsutiya, and G. Goto: “Possibility and Limitation of Wafer Scale LSI”, NIKKEI ELECTRONICS, no.422, pp.141-161, 1987. (in Japanese).Google Scholar
  6. 6.
    R. Negrini, M.G. Sami, and R. Stefanelli: “Fault-Tolerant Through Reconfiguration of VLSI and WSI Arrays”, The MIT Press, 1989.Google Scholar
  7. 7.
    E. Swartlander and J. Brewer (ed.): “International Conference on Wafer Scale Integration”, Computer Society Press, 1989.Google Scholar
  8. 8.
    S.K. Tewksbury: “Wafer-Level Integrated Systems: Implementation Issues”, Kluwer Academic Publishers, 1989.Google Scholar
  9. 9.
    M. Tarr, D. Boudreau, and R. Murphy: “Defect Analysis System Speeds Test and Repair of Redundant Memories”, Electronics, Vol.12, pp.175-179, Jan. 1984.Google Scholar
  10. 10.
    F.T. Leighton and C.E. Leiserson: “Wafer-Scale Integration of Systolic Arrays”, IEEE Trans. Comput., Vol.C-34, No.5, pp.448–461, 1985.CrossRefGoogle Scholar
  11. 11.
    T. Satoh and N. Tsuda: “Hierachical Redundancy for One-dimensional Array Logics”, IECE Japan, Paper of Technical Group, FTS87-4, pp.27-33, 1987. (in Japanese).Google Scholar
  12. 12.
    K. Hashino, K. Hagihara, and N. Tokura: “Fault-Tolerant WSI Processor Arrays using Hyper-graph Approach”, IECE Japan, Paper of Technical Group, COMP87-30, pp.41-52, 1987. (in Japanese).Google Scholar
  13. 13.
    P. Banerjee, Sy-Yen Kuo, and W.K. Fuchs: “Reconfigurable Cube-Connected Cycles Architectures”, Proc. 16th Int’l Symp. Fault-Tolerant Computing, pp.286-291, 1986.Google Scholar
  14. 14.
    A.L. Rosenberg: “Graph-Theoretic Approaches to Fault-Tolerant WSI Processor Arrays “, Wafer Scale Integration Proceedings of a Workshop held in Southampton, 1985, Adam Hilger, pp.10-23, 1986.Google Scholar
  15. 15.
    A.L. Rosenberg: “A Hypergraph Model for Fault-Tolerant VLSI Processor Arrays”, IEEE Trans. Comput., C-34, no.6, pp.578–584, 1985.CrossRefGoogle Scholar
  16. 16.
    A.L. Rosenberg: “The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors”, IEEE Trans. Comput., C-32, No.8, pp.902–910, 1983.CrossRefGoogle Scholar
  17. 17.
    F.R.K. Chung, F.T. Leighton, and A.L. Rosenberg: “DIOGENES: A Methodology for Designing Fault-Tolerant Processor Arrays”, Proc. 13th Int. Conf. on Fanlt-Tolerant Computing, pp.26-32, 1983.Google Scholar
  18. 18.
    L.N. Bhuyan and D.P. Agrawal: “Generalized Hypercube and Hyperbus Structures for a Computer Network”, IEEE Trans. Comput., C-33, No.4, pp.323–333, 1984.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • H. Ito
    • 1
  • N. Suzuki
    • 1
  1. 1.Dept. of Electrical and Electronics Engr.Chiba University1-33 Yayoi-cho, Chiba-shiJapan

Personalised recommendations