Fast and efficient testing is an important step in any manufacturing process. With the recent advances in semiconductor technology, the design and use of memories for realizing complex systems-on-a-chip has been widespread. The cost of testing such memories increases rapidly with every generation. Precise and realistic fault modeling, and efficient test design, in order to keep test cost and time within economically acceptable limits, are therefore essential.
KeywordsMemory Device Fault Model Fault Coverage Static Random Access Memory SRAM Cell
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