A Complete Design Modeled with SystemVerilog
This chapter brings together the many concepts presented in previous chapters of this book, and shows how the SystemVerilog enhancements to Verilog can be used to model large designs much more efficiently than with the standard Verilog HDL. The example presented in this chapter shows how SystemVerilog can be used to model at a much higher level of data abstraction than Verilog, and yet be fully synthesizable.
KeywordsAsynchronous Transfer Mode Forwarding Node Packet Type Packed Union Test View
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