Intermediate Memory Device

  • A. M. Goryachev
  • V. A. Zapevalov
Part of the The Lebedev Physics Institute Series book series (LPIS, volume 54)

Abstract

The logic circuits distributing read and write pulses over the rows of an intermediate core are described. The incoming five-digit binary code is written into the first unfilled row, whereas writing is effected from the first filled row.

Keywords

Logic Circuit Logic Expression Logic Block Photonuclear Reaction Recording Equipment 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    R. E. Bell, Canad. I. Phys., 34: 563 (1956).ADSCrossRefGoogle Scholar
  2. 2.
    I. V. Shtranikh, Reports of the 5th Scientific-Technological Conference on Nuclear Electronics, Vol. 2, Part 1, p. 47 [in Russian], Atomizdat (1963).Google Scholar
  3. 3.
    B. E. Zhuravlev, T. Shetet, and V. D. Shibaev, Preprint OIYaI 10–3120 [in Russian], Dubna (1967).Google Scholar

Copyright information

© Springer Science+Business Media New York 1974

Authors and Affiliations

  • A. M. Goryachev
  • V. A. Zapevalov

There are no affiliations available

Personalised recommendations