Switch-Level Timing Simulation

  • Resve Saleh
  • Shyh-Jye Jou
  • A. Richard Newton
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 279)

Abstract

Most modern logic simulators handle the problems specific to MOS integrated circuits by including the notion of signal strength in the logic model. However, the use of strength does not, by itself, solve all the modeling problems inherent to MOS circuits. For example, circuit designers use many combinations of transistors which do not have a direct mapping to a logic gate and therefore cannot be represented conveniently at the gate level. It is also difficult to model the logic operation of dynamic circuits in a convenient form in a standard logic simulator. Transfer gates further complicate the situation because they introduce dynamic loading effects, bidirectional signal flow, and capacitive charge-sharing effects. Many of these problems were resolved with the advent of the switch-level modeling and simulation technique [BRY80].

Keywords

Logic Gate Logic Level Gate Input Waveform Relaxation Logic Simulation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media New York 1994

Authors and Affiliations

  • Resve Saleh
    • 1
  • Shyh-Jye Jou
    • 1
  • A. Richard Newton
    • 2
  1. 1.University of IllinoisUSA
  2. 2.University of CaliforniaUSA

Personalised recommendations