Defect Oriented RAM Testing and Current Testable RAMs

  • Manoj Sachdev
Part of the Frontiers in Electronic Testing book series (FRET, volume 10)

Abstract

RAMs are integral building blocks of modern ICs and systems. As far as the testing is concerned, RAMs suffer from quantitative issues of digital testing along with the qualitative issues of analog testing. This chapter reviews the state of the art of defect oriented testing of RAMs and proposes a RAM test methodology using IDDQ and voltage based march tests. Bridging defects in a RAM matrix, including the gate oxide defects, are detected by four IDDQ measurements. The IDDQ test is then supplemented with voltage based march test to detect the defects (opens and data retention) not detectable by the IDDQ technique. The combined test methodology reduces the algorithmic test complexity substantially.

Keywords

Fault Model Test Algorithm Read Operation Open Defect NAND Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    M.S. Abadir and H.K. Reghbati, “Functional Testing of Semiconductor Random Access Memories,” ACM Computing Surveys, vol. 25, no. 3, pp. 175–198, September 1983.CrossRefGoogle Scholar
  2. 2.
    M.A. Breuer and A.D. Friedman, Diagnosis and Reliable Design of Digital Systems, Rockville, MD: Computer Science Press, 1976.CrossRefGoogle Scholar
  3. 3.
    E.M.J.G. Bruis, “Reliability Aspects of Defects Analysis,” Proceedings of European Test Conference, 1993, pp. 17–26.Google Scholar
  4. 4.
    R. Dekker, F. Beenker and L. Thijssen, “Fault Modeling and Test Algorithm Development for Static Random Access Memories,” Proceedings of International Test Conference, 1988, pp. 343–352.Google Scholar
  5. 5.
    B.N. Dostie, A. Silburt and V.K. Agarwal, “Serial Interfacing for Embedded-Memory Testing,” IEEE Design & Test of Computers, vol. 7, pp. 52–63, April 1990.CrossRefGoogle Scholar
  6. 6.
    F.J. Ferguson, and J.P. Shen, “Extraction and simulation of realistic CMOS faults using inductive fault analysis,” Proceedings of International Test Conference, 1988, pp. 475–484.Google Scholar
  7. 7.
    A.V. Ferris-Prabhu, “Computation of the critical area in semiconductor yield theory,” Proceedings of the European Conference on Electronic Design Automation, 1984, pp. 171–173Google Scholar
  8. 8.
    M. Franklin, K.K. Saluja and K. Kinoshita, “Design of a BIST RAM with Row/ Column Pattern Sensitive Fault Detection Capability,” Proceedings of International Test Conference, 1989, pp. 327–336.Google Scholar
  9. 9.
    M. Franklin, K.K. Saluja and K. Kinoshita, “Row/Column Pattern Sensitive Fault Detection in RAMs via Built-in Self-Test,” Proceedings of Fault Tolerant Computing Symposium, June 1989, pp. 36–43.Google Scholar
  10. 10.
    M. Franklin, K.K. Saluja, and K. Kinoshita, “A Built-In Self-Test Algorithm for Row/Column Pattern Sensitive Faults in RAMs,” IEEE Journal of Solid State Circuits, vol. 25, no. 2, pp. 514–523, April 1990.CrossRefGoogle Scholar
  11. 11.
    A.J. van de Goor, Testing Semiconductor Memories, Theory and Practice, John Wiley and Sons, 1991.Google Scholar
  12. 12.
    T. Guckert, P. Schani, M. Philips, M. Seeley and H. Herr, “Design and Process Issues for Elimination of Device Failures Due to ‘Drooping’ Vias,” Proceedings of International Symposium for Testing and Failure Analysis (ISTFA), 1991, pp. 443451.Google Scholar
  13. 13.
    J.P. Hayes, “Detection of Pattern-Sensitive Faults in Random Access Memories,” IEEE Transactions on Computers, vol. 24, no. 2, pp. 150–157, February 1975.MathSciNetMATHCrossRefGoogle Scholar
  14. 14.
    J.P. Hayes, “Testing Memories for Single-Cell Pattern-Sensitive Faults,” IEEE Transactions on Computers, vol. 29, no. 3, pp. 249–254, March 1980.MathSciNetMATHCrossRefGoogle Scholar
  15. 15.
    L. K. Horning, J.M. Soden, R.R. Fritzemeier and C.F. Hawkins, “Measurements of Quiescent Power Supply Current for CMOS ICs in Production Testing,” Proceedings of International Test Conference, 1987, pp. 300–309.Google Scholar
  16. 16.
    J. Inoue, T. Matsumura, M. Tanno and J. Yamada, “Parallel Testing Technology for VLSI Memories,” Proceedings of International Test Conference, 1987, pp. 1066–1071.Google Scholar
  17. 17.
    M. Inoue, T. Yamada and A. Fujiwara, “A New Testing Acceleration Chip for Low-Cost Memory Test,” IEEE Design & Test of computers, vol. 10, pp. 15–19, March 1993.CrossRefGoogle Scholar
  18. 18.
    J. Knaizuk and C.R.P. Hartman, “An Optimal Algorithm for Testing Stuck-At Faults in Random Access Memories,” IEEE Transactions on Computers, vol. 26, no. 11, pp. 1141–1144, November 1977.CrossRefGoogle Scholar
  19. 19.
    S. Koeppe, “Optimal layout to avoid CMOS stuck-open faults,” Proceedings of 24th Design Automation Conference, 1987, pp. 829–835.Google Scholar
  20. 20.
    M. Kumanoya, et al., “A 90ns 1Mb DRAM with Multi-Bit Test Mode,” International Solid State Circuits Conference: Digest of Technical Papers, 1985, pp. 240241.Google Scholar
  21. 21.
    K.J. Lee and M.A. Breuer, “Design and Test Rules for CMOS Circuits to Facilitate IDDQ Testing of Bridging Faults,” IEEE Transactions on Computer-Aided Design, vol. 11, no. 5, pp. 659–669, May 1992.CrossRefGoogle Scholar
  22. 22.
    M.E. Levitt and J.A. Abraham, “Physical Design of Testable VLSI: Techniques and Experiments,” IEEE Journal of Solid State Circuits, vol. 25, no. 2, pp. 474–481, April 1990.CrossRefGoogle Scholar
  23. 23.
    W. Maly, “Realistic Fault Modeling for VLSI Testing,” Proceedings of 24th ACM/ IEEE Design Automation Conference, 1987, pp. 173–180.Google Scholar
  24. 24.
    W. Maly and M. Patyra, “Design of ICs Applying Built-in Current Testing,” Journal of Electronic Testing: Theory and Applications, vol. 3, pp. 397–406, November 1992.CrossRefGoogle Scholar
  25. 25.
    Y. Matsuda, et al., “A New Parallel Array Architecture For Parallel Testing in VLSI Memories,” Proceedings of International Test Conference, 1989, pp. 322–326.Google Scholar
  26. 26.
    P. Mazumder, “Parallel Testing of Parametric Faults in Three Dimensional Random Access Memory,” IEEE Journal of Solid State Circuits, vol. 23, pp. 933–941, 1988.CrossRefGoogle Scholar
  27. 27.
    P. Mazumder and K. Chakraborty, Testing and Testable Design of High-Density Random-Access Memories, Boston: Kluwer Academic Publishers, 1996.CrossRefGoogle Scholar
  28. 28.
    H. McAdams, et al., “A 1-Mbit CMOS Dynamic RAM with Design For Test Functions,” IEEE Journal of Solid State Circuits, vol. 21, pp. 635–641, October 1986.CrossRefGoogle Scholar
  29. 29.
    R. Meershoek, B. Verhelst, R. McInerney and L. Thijssen, “Functional and Iddq Testing on a Static RAM,” Proceedings of International Test Conference, 1990, pp. 929–937.Google Scholar
  30. 30.
    A. Meixner and W. Maly, “Fault Modeling for the Testing of Mixed Integrated Circuits,” Proceedings of International Test Conference, 1991, pp. 564–572.Google Scholar
  31. 31.
    S. Naik, F. Agricola and W. Maly, “Failure analysis of High Density CMOS SRAMs Using Realistic Defect Modeling and IDDQ Testing,” IEEE Design & Test of Computers, vol. 10, pp. 13–23, June 1993.CrossRefGoogle Scholar
  32. 32.
    R. Nair, “Comments on an Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories,” IEEE Transactions on Computers, vol. 28, no. 3, pp. 258–261, March 1979.CrossRefGoogle Scholar
  33. 33.
    R. Nair, S.M. Thatte and J.A. Abraham, “Efficient Algorithms for Testing Semiconductor Random Access Memories,” IEEE Transactions on Computers, vol. 27, no. 6, pp. 572–576, June 1978.MathSciNetMATHCrossRefGoogle Scholar
  34. 34.
    H.D. Oberle and P. Muhmenthaler, “Test Pattern-Development and Evaluation for DRAMs with Fault Simulator RAMSIM,” Proceedings of International Test Conference, 1991, pp. 548–555.Google Scholar
  35. 35.
    C.A. Papachristou and N.B. Sahgal, “An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories,” IEEE Transactions on Computers, vol. 34, no. 2, pp. 110–116, February 1985.CrossRefGoogle Scholar
  36. 36.
    R. Perry, “IDDQ testing in CMOS digital ASICs,” Journal of Electronic Testing: Theory and Applications, vol. 3, pp. 317–325, November 1992.CrossRefGoogle Scholar
  37. 37.
    B. Prince, Semiconductor Memories, Chichester, UK: John Wiley and Sons, 1991.Google Scholar
  38. 38.
    M. A. Rich and D. E. Gentry, “The Economics of Parallel Testing,” Proceedings of International Test Conference, 1983, pp. 728–737.Google Scholar
  39. 39.
    M. Sachdev and M. Verstraelen, “Development of a Fault Model and Test Algorithms for Embedded DRAMs,” Proceedings of the International Test Conference, 1993, pp. 815–824.Google Scholar
  40. 40.
    M. Sachdev, “Transforming Sequential Logic in Digital CMOS ICs for Voltage and IppQ Testing,” Proceedings of European Design and Test Conference, 1994, pp. 361–365.Google Scholar
  41. 41.
    M. Sachdev, “Reducing the CMOS RAM Test Complexity with IppQ and Voltage Testing,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 6, no. 2, pp. 191–202, April 1995.MathSciNetCrossRefGoogle Scholar
  42. 42.
    J. Savir, W.H. McAnney and S.R. Vecchio, “Testing for Coupled Cells in Random Access Memories,” Proceedings of International Test Conference, 1989, pp. 439–451.Google Scholar
  43. 43.
    Semiconductor Industry Association (SIA), “The National Technology Roadmap for Semiconductors, ” pp. 94–99, 1994.Google Scholar
  44. 44.
    A. H. Shah, et al., `A 4-Mbit DRAM with Trench Transistor Cell,“ IEEE Journal of Solid State Circuits, vol. SC-21, pp. 618–627, October 1986.Google Scholar
  45. 45.
    J.P. Shen, W. Maly and F.J. Ferguson, “Inductive Fault Analysis of MOS Integrated Circuits,” IEEE Design & Test of Computers, vol. 2, no. 6, pp. 13–26, 1985.CrossRefGoogle Scholar
  46. 46.
    J.M. Soden, C.F. Hawkins, R.K. Gulati and W. Mao, “IDDQ Testing: A Review,” Journal of Electronic Testing: Theory and Applications, vol. 3, pp. 291–303, November 1992.CrossRefGoogle Scholar
  47. 47.
    T. Sridhar, “A New Parallel Test Approach for Large Memories,” Proceedings of International Test Conference, 1985, pp. 462–470.Google Scholar
  48. 48.
    F.A. Steenhof, C.G. van der Sanden and B.C. Pham, “Design Principles of a DRAM Cell Matrix for Embedded Applications,” Nat.Lab. internal technical note, TN 250/90.Google Scholar
  49. 49.
    S.T. Su and R.Z. Makki, “Testing of Static Random Access Memories by Monitoring Dynamic Power Supply Current,” Journal of Electronic Testing: Theory and Applications, vol. 3, pp. 265–278, August 1992.CrossRefGoogle Scholar
  50. 50.
    D.S. Suk and S.M. Reddy, “Test Procedure for a Class of Pattern-Sensitive Faults in Random Access Memories,” IEEE Transactions on Computers, vol. 29, no. 3, pp. 419–429, June 1980.MATHCrossRefGoogle Scholar
  51. 51.
    D.S. Suk and S.M. Reddy, “A March Test for Functional Faults in Semiconductor Random Access Memories,” IEEE Transactions on Computers, vol. 30, no. 12, pp. 982–985, December 1981.CrossRefGoogle Scholar
  52. 52.
    M. Syrzycki, “Modeling of Spot Defects in MOS Transistors,” Proceedings of International Test Conference, 1987, pp. 148–157.Google Scholar
  53. 53.
    E. Takeda, et al., “VLSI Reliability Challenges: From Device Physics to Wafer Scale Systems,” Proceedings of IEEE, vol. 81, no. 5, 1993, pp. 653–674.CrossRefGoogle Scholar
  54. 54.
    S.M. Thatte and J.A. Abraham, “Testing of Semiconductor Random Access Memories,” Proceedings of Fault Tolerant Computing Symposium, 1977, pp. 81–87.Google Scholar
  55. 55.
    H. Walker and S.W. Director, “VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 5, no. 4, pp. 541–556, 1986.CrossRefGoogle Scholar
  56. 56.
    H. Yokoyama, H. Tamamoto and Y. Narita, “A Current Testing for CMOS Static RAMs,” Proceedings of IEEE International Workshop on Memory Technology, Design and Testing, August 1993, pp. 137–142.Google Scholar
  57. 57.
    Y. You and J.P. Hayes, “A Self Testing Dynamic RAM Chip,” IEEE Journal of Solid State Circuits, vol. 20, no. 1, pp. 428–435, February 1985.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • Manoj Sachdev
    • 1
  1. 1.Philips ResearchThe Netherlands

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