# Digital CMOS Fault Modeling and Inductive Fault Analysis

Chapter

## Abstract

We begin with an overview of digital fault models. Different fault models are classified according to the level of abstraction. The merits and shortcomings of these models are reviewed. The second half of the chapter is devoted to the defect oriented fault modeling methodology or Inductive Fault Analysis, as it is popularly known. Unlike the conventional fault modeling methods, IFA takes into account the circuit layout and manufacturing process defects to generate realistic and layout dependent faults.

## Keywords

Fault Modeling Logic Gate Test Vector NAND Gate Delay Fault
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## References

- 1.M.S. Abadir, and H.K. Reghbati, “Functional Testing of Semiconductor Random Access Memories,”
*ACM Computing Surveys*, 15 (3), pp. 175–198, Sept. 1983.CrossRefGoogle Scholar - 2.J. A. Abraham, “Fault Modeling in VLSI,” in
*VLSI Testing, Edited by T.W. Williams*, vol. 5, North-Holland, pp. 1–27, 1986.Google Scholar - 3.V.D. Agrawal, “Synchronous Path Analysis in MOS Circuit Simulator,”
*Proc. of 19th Design Automation Conf.*, June 1982, pp. 629–635.Google Scholar - 4.H.B. Bakoglu and J.D. Meindel, “Optimal Interconnection Circuits for VLSI,”
*IEEE Transactions on Electron Devices*, vol. ED-32, no. 5, pp. 903–909, May 1985.Google Scholar - 5.P. Banerjee and J.A. Abraham, “Characterization and Testing of Physical Failures in MOS Logic Circuits,”
*IEEE Design & Test of Computers*, vol. 1, pp. 76–86, August 1984.CrossRefGoogle Scholar - 6.F.P.M. Beenker, K.J.E. van Eerdewijk, R.B.W. Gerritsen, F.N. Peacock and M. van der Star, “Macro Testing, Unifying IC and Board Test,”
*IEEE Design and Test of Computers*, vol. 3, pp. 26–32, December 1986.CrossRefGoogle Scholar - 7.S. Bothra, B. Rogers, M. kellern and C.M. Osburn, Analysis of the Effects of Scaling on Interconnect Delay in ULSI Circuits,“
*IEEE Transactions on Electron Devices*, vol. ED-40, no. 3, pp. 591–597, March 1993.Google Scholar - 8.D.S. Brahme and J.A. Abraham, “Functional Testing of Microprocessors,”
*IEEE Transactions on Computers*, vol. C-33, pp. 475–485, 1984.Google Scholar - 9.M.A. Breuer and A.D. Friedman,
*Diagnosis and Reliable Design of Digital Systems*, Woodland Hills, California: Computer Science Press, 1976.CrossRefGoogle Scholar - 10.T.J. Chakraborty, V.D. Agrawal and M.L. Bushnell, “Delay Fault Models and Test Generation for Random Logic Sequential Circuits,”
*Proc. 29th Design Automation Conf*, June 1992, pp. 165–172.Google Scholar - 11.R. Chandramouli, “On Testing Stuck-Open Faults,”
*Proceedings of 13th Annual International Symposium on Fault Tolerant Computing Systems*,1983, pp. 258265.Google Scholar - 12.K.T. Chang and H.C. Chen, “Classification and Identification of Nonrobust Untestabel path Delay Faults,”
*IEEE Transactions on CAD*, vol. 15, pp. 845–853, August 1996.CrossRefGoogle Scholar - 13.K.T. Cheng, “Transition Fault Simulation for Sequential Circuits,”
*Proceedings of International Test Conference*, 1992, pp. 723–731.Google Scholar - 14.B.F. Cockburn, “Tutorial on Semiconductor Memory Testing,”
*Journal of Electronic Testing: Theory and Applications (JETTA)*, vol. 5, no. 4, pp. 321–336, November 1994.MathSciNetCrossRefGoogle Scholar - 15.H. Cox and J. Rajaski, “Stuck-Open and Transition Fault Testing in CMOS Complex Gates,”
*Proceedings of International Test Conference*, 1988, pp. 688–694.Google Scholar - 16.R. Dekker, F. Beenker and L. Thijssen, “Fault modeling and Test Algorithm Development for Static Random Access Memories,”
*Proceedings of International Test Conference*, 1988, pp. 343–352.Google Scholar - 17.C. Di and J.A.G. Jess, “On Accurate Modeling and Efficient Simulation of CMOS Open Faults,”
*Proceedings of International Test Conference*, 1993, pp. 875–882.Google Scholar - 18.E.B. Eichelberger and T.W. Williams, “A Logic Design Structure for LSI Testability,”
*Journal of Design Automation and Fault Tolerant Computing*, vol. 2, no. 2, pp. 165–178, May 1978.Google Scholar - 19.R.D. Eldred, “Test Routines Based on Symbolic Logical Statements,”
*Journal of ACM*, vol. 6, no. 1, pp. 33–36, January 1959.MathSciNetMATHCrossRefGoogle Scholar - 20.Y.M. El-Ziq and R.J. Cloutier, “Functional-Level Test Generation for Stuck-Open Faults in CMOS VLSI,”
*PrOceedings of International Test Conference*, 1981, pp. 536–546.Google Scholar - 21.F.J. Ferguson and J.P. Shen, “Extraction and Simulation of Realistic CMOS Faults using Inductive Fault Analysis,”
*Proceedings of International Test Conference*, 1988, pp. 475–484.Google Scholar - 22.A.V. Ferris-Prabhu,
*Introduction to Semiconductor Device Yield Modeling*, Boston: Artech House, 1992.Google Scholar - 23.M.L. Flottes, C. Landrault and S. Pravossoudovitch, “Fault Modeling and Fault Equivalence in CMOS Technology,”
*Journal of Electronic Testing: Theory and Applications*, vol. 2, no. 3, pp. 229–241, August 1991.CrossRefGoogle Scholar - 24.S. Funatsu, N. Wakatsuki and T. Arima, “Test Generation Systems in Japan,”
*Proceedings of 12th Design Automation Symposium*, 1975, pp. 114–122.Google Scholar - 25.D. Gaitonde and D.H.H. Walker, “Test Quality and Yield Analysis Using the DEFAM Defect to Fault Mapper,”
*Proceedings of International Conference on Computer Aided Design*, 1993, pp. 202–205.Google Scholar - 26.J. Galiay, Y. Crouzet and M. Vergniault, “Physical Versus Logical Fault Models in MOS LSI Circuits: Impact on Their Testability,”
*IEEE Transaction on Computers*, vol. C-29, no. 6, pp. 527–531, June 1980.Google Scholar - 27.S.K. Gandhi,
*VLSI Fabrication Principles*, John Wiley and Sons, 1983.Google Scholar - 28.D.S. Gardner, J.D. Meindel and K.C. Saraswat, “Interconnection and Electromigration Scaling Theory,”
*IEEE Transactions on Electron Devices*, vol. ED-34, no. 3, pp. 633–643, March 1987.CrossRefGoogle Scholar - 29.A.J. van de Goor,
*Testing Semiconductor Memories: Theory and Practices*,John Wiley and Sons, 1991.Google Scholar - 30.A. Goundan and J.P. Hayes, “Identification of Equivalent Faults in Logic Networks,”
*IEEE Transactions on Computers*, vol. c-29, no. 11, pp. 978–985, November 1980.Google Scholar - 31.J.P. Hayes, “Fault Modeling for Digital Integrated Circuits,”
*IEEE Transactions on Computer-Aided Design of Circuits and Systems*, CAD-3, pp. 200–207, 1984.Google Scholar - 32.J.P. Hayes, “Fault Modeling,”
*IEEE Design & Test of Computers*, vol. 2, pp. 88–95, April 1985.Google Scholar - 33.J.P. Hayes, “Detection of Pattern-Sensitive Faults in Random Access Memories,”
*IEEE Transactions on Computers*, vol. C-24, no. 2, pp. 150–157, February 1975.Google Scholar - 34.R.J.A. Harvey, A.M.D. Richardson, E.M.J. Bruis and K. Baker, “Analogue Fault Simulation Based on Layout Dependent Fault Models,”
*Proceedings of International Test Conference*, 1994, pp. 641–649.Google Scholar - 35.O.H. Ibarra and S.K. Sahni, “Polynomial Complete Fault Detection Problems,”
*IEEE Transactions on Computers*, vol. c-24, no. 3, pp. 242–249, March 1975.Google Scholar - 36.V.S. Iyenger et al., “On Computing the Sizes of Detected Delay Faults,”
*IEEE Transactions on CAD*, vol. 9, no. 3, 299–312, 1990.CrossRefGoogle Scholar - 37.S.K. Jain and V.D. Agrawal, “Modeling and Test Generation Algorithm for MOS Circuits,”
*IEEE Transactions on Computers*, vol. 34, no. 5, pp. 426–43, May 1985.CrossRefGoogle Scholar - 38.A.P. Jayasumana, Y.K. Malaiya and R. Rajsuman, “Design of CMOS Circuits for Stuck-Open Fault Testability,”
*IEEE Journal of Solid-State Circuits*, vol. 26, no. 1, pp. 58–61, January 1991.CrossRefGoogle Scholar - 39.W. Ke and P.R. Menon, “Synthesis of Delay Verifiable Combinational Circuits,”
*IEEE Transactions on Computers*, vol. 44, pp. 213–222, February 1995.CrossRefGoogle Scholar - 40.S. Koeppe, “Optimum Layout to Avoid CMOS Stuk-Open Fault,”
*Proceedings of 24th ACM/IEEE Design Automation Conference*, 1987, pp. 829–835.Google Scholar - 41.F.C.M. Kuijstermans, M. Sachdev and L. Thijssen, “Defect Oriented Test Methodology for Complex Mixed-Signal Circuits,”
*Proceedings of European Design and Test Conference*, 1995, pp. 18–23.Google Scholar - 42.W.K. Lam, A. Saldanha, R.K. Brayton and A.L. Sangiovanni-Vincentelli, “Delay Fault Coverage and Performance Trade-offs,”
*Proceedings of 30th Design Automation Conference*, 1993, pp. 446–452.Google Scholar - 43.K.J. Lee and M.A. Breuer, “On the Charge Sharing Problem in CMOS Stuck-Open Fault Testing,”
*Proceedings of International Test Conference*,1990, pp. 417425.Google Scholar - 44.A.K. Majhi, J. Jacob, L.M. Patnaik and V.D. Agrawal, “On Test Coverage of Path Delay Faults,”
*Proc. of 9th International Conference on VLSI Design*, January 1996, pp. 418–421.Google Scholar - 45.P. Mazumder and K. Chakraborty,
*Testing and Testable Design of High-Density Random-Access Memories*, Boston: Kluwer Academic Publishers, 1996.CrossRefGoogle Scholar - 46.Y.K. Malaiya and R. Narayanaswamy, “Modeling and Testing for Timing Faults in Synchronous Sequential Circuits,”
*IEEE Design & Test of Computers*, vol. 1, no. 4, pp. 62–74, November 1984.CrossRefGoogle Scholar - 47.W. Maly, F.J. Ferguson and J.P. Shen, “Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells,”
*Proceedings of International Test Conference*, 1984, 390–399.Google Scholar - 48.W. Maly, W.R. Moore and A.J. Strojwas, “Yield Loss Mechanisms and Defect Tolerance,” SRC-CMU Research Center for Computer Aided Design, Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213.Google Scholar
- 49.W. Maly, A.J. Strojwas and S.W. Director, “VLSI Yield Prediction and Estimation: A Unified Framework,”
*IEEE Transaction on Computer Aided Design*, vol. CADS, no. 1, pp. 114–130, January 1986.Google Scholar - 50.W. Mao, R. Gulati, D.K. Goel and M.D. Ciletti, “QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults,”
*Proceedings of International Conference on CAD*, 1990, pp. 280–283.Google Scholar - 51.E.J. McCluskey and F.W. Clegg, “Fault Equivalence in Combinational Logic Networks,”
*IEEE Transactions on Computers*, vol. c-20, no. 11, pp. 1286–1293, November 1971.Google Scholar - 52.A. Meixner and W. Maly, “Fault Modeling for the Testing of Mixed Integrated Circuits,”
*Proceedings of International Test Conference*, 1991, pp. 564–572.Google Scholar - 53.S. Mourad and E.J. McCluskey, “Fault Models,”
*Testing and Diagnosis of VLSI and ULSI*, Boston: Kluwer Academic Publishers, pp. 49–68, 1989.Google Scholar - 54.P. Nigh and W. Maly, “Test Generation for Current Testing,”
*IEEE Design & Test of Computers*, pp. 26–38, February 1990.Google Scholar - 55.E.S. Park, B. Underwood, T.W. Williams and M.R. Mercer, “Delay Testing Quality in Timing-Optimized Designs,”
*Proceedings of International Test Conference*, 1991, pp. 879–905.Google Scholar - 56.E.S. Park and M.R. Mercer, “An Efficient Delay Test Generation System for Combinational Logic Circuits,”
*IEEE Transactions on CAD*, vol. 11, pp. 926–938, July 1992.CrossRefGoogle Scholar - 57.C.A. Papachristou and N.B. Sahgal, “An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories,”
*IEEE Transactions on Computers*, vol. C-34, no. 2, pp. 110–116, February 1985.Google Scholar - 58.A. Pierzynska and S. Pilarski, “Non-Robust versus Robust,”
*Proceedings of International Test Conference*, 1995, pp. 123–131.Google Scholar - 59.J.F. Poage, “Derivation of Optimum Tests to Detect Faults in Combinational Circuits,”
*Proceedings of Symposium on Mathematical Theory of Automata*,1963, pp. 483–528Google Scholar - 60.A.K. Pramanick and S.M. Reddy, “On the Computation of the Ranges of Detected Delay Fault Sizes,”
*IEEE International Conference on CAD*, pp. 126–129, 1989.Google Scholar - 61.I. Pramanick and A.K. Pramanick, “Parallel Delay Fault Coverage and Test Quality Evaluation,”
*Proceedings of International Test Conference*, 1995, pp. 113–122.Google Scholar - 62.B. Prince,
*Semiconductor Memories*, John Wiley and Sons, 1991.Google Scholar - 63.R. Rajsuman, A.P. Jayasumana and Y.K. Malaiya, “CMOS Stuck-Open Fault Detection Using Single Test Patterns,”
*Proceedings of ACM/IEEE Design Automation Conference*, 1989, pp. 714–717.Google Scholar - 64.R. Rajsuman, A.P. Jayasumana and Y.K. Malaiya, “CMOS Open-Fault Detection in the Presence of Glitches and Timing Skews,”
*IEEE Journal of Solid-State Circuits*, vol. 24, no. 4, pp. 1129–1136, August 1989.CrossRefGoogle Scholar - 65.S.M. Reddy and S. Kundu, “Fault Detection and Design For Testability of CMOS Logic Circuits,”
*Testing and Diagnosis of VLSI and VLSI*, Edited by F. Lombardi and M. Sami, pp. 69–91, 1989.Google Scholar - 66.S.M. Reddy, M.K. Reddy and J.G. Kuhl, “On Testable Design for CMOS Logic Circuits,”
*Proceedings of International Test Conference*, 1983, 435–445.Google Scholar - 67.S.M. Reddy, M.K. Reddy and V.D. Agrawal, “Robust Test for Stuck-Open Faults in CMOS Combinational Logic Circuits,”
*Proceedings of 14th International Symposium on Fault Tolerant Computing*, 1984, pp. 44–49.Google Scholar - 68.B.K. Roy, “Diagnosis and Fault Equivalence in Combinational Circuits,”
*IEEE Transactions on Computers*, vol. c-23, no. 9, pp. 955–963, September 1974.Google Scholar - 69.M. Sachdev and M. Verstraelen, “Development of a Fault Model and Test Algorithms for Embedded DRAMs,”
*Proceedings of International Test Conference*, 1993, pp. 815–824.Google Scholar - 70.M. Sachdev, “Defect Oriented Analog Testing: Strengths and Weaknesses,”
*Proceedings of 20th European Solid State Circuits Conference*, 1994, pp. 224–227.Google Scholar - 71.M. Sachdev, “A Defect Oriented Testability Methodology for Analog Circuits,”
*Journal of Electronic Testing: Theory and Applications*, vol. 6, pp. 265–276, June 1995.CrossRefGoogle Scholar - 72.M. Sachdev, “Reducing the CMOS RAM Test Complexity with IDDQ and Voltage Testing,”
*Journal of Electronic Testing: Theory and Applications (JE77’A)*, vol. 6, no. 2, pp. 191–202, April 1995.MathSciNetCrossRefGoogle Scholar - 73.K.C. Saraswat and F. Mohammadi, “Effect of Scaling of Interconnections on the Time Delay of VLSI Circuits,”
*IEEE Transactions on Electron Devices*, vol. ED-29, no. 4, pp. 645–650, April 1982.Google Scholar - 74.J. Savir, W.H. McAnney and S.R. Vecchio, “Testing for Coupled Cells in Random Access Memories,”
*Proceedings of International Test Conference*,1989, pp. 439451.Google Scholar - 75.D.R. Schertz and G. Metze, `A New Representation for Faults in Combinational Digital Circuits,“
*IEEE Transactions on Computers*, vol. c-21, no. 8, pp. 858–866, August 1972.Google Scholar - 76.J.P. Shen, W. Maly and F.J. Ferguson, “Inductive Fault Analysis of MOS Integrated Circuits,”
*IEEE Design & Test of Computers*, vol. 2, pp. 13–26, December 1985.CrossRefGoogle Scholar - 77.H.C. Shih and J.A. Abraham, “Fault Collapsing Techniques for MOS VLSI Circuits,”
*Proceedings of Fault Tolerant Computing Symposium*, 1986, pp. 370–375.Google Scholar - 78.M. Sivaraman and A.J. Strojwas, “Test Vector Generation for Parametric Path Delay Faults,”
*Proceedings of International Test Conference*, 1995, pp. 132–138.Google Scholar - 79.J.E. Smith, “Detection of Faults in Programmable Logic Arrays IEEE Transactions on Computers,vol. C-28, pp. 845–853, 1979.Google Scholar
- 80.G.L. Smith, “Model for Delay Faults Based upon Paths Proceedings of International Test Conference,1985, pp. 342–349.Google Scholar
- 81.J.M. Soden, C.F. Hawkins, R.K. Gulati and W. Mao, “IDDQ Testing: A Review,”
*Journal of Electronic Testing: Theory and Applications*, vol. 3, pp. 291–303, November 1992.CrossRefGoogle Scholar - 82.M. Soma, “An Experimental Approach to Analog Fault Models Proceedings of Custom Integrated Circuits Conference,1991, pp. 13.6.1–13.6.4.Google Scholar
- 83.M. Soma, “A Design for Test Methodology for Active Analog Filters Proceedings of International Test Conference,1990, pp. 183–192.Google Scholar
- 84.M. Soma, “Fault Modeling and Test Generation for Sample and Hold Circuit,”
*Proceedings of International Symposium on Circuits and Systems*,1991, pp. 20722075.Google Scholar - 85.D.S. Suk and S.M. Reddy, “A March Test for Functional Faults in Semiconductor Random Access Memories,”
*IEEE Transactions on Computers*, vol. C-30, no. 12, pp. 982–985, Dec. 1981.Google Scholar - 86.S.M. Sze,
*VLSI Technology*, New York: McGraw Hill Book Company 1983.Google Scholar - 87.S.M. Thatte and J.A. Abraham, “Testing of Semiconductor Random Access Memories,”
*Proceedings of International Conference on Fault Tolerant Computing*, 1977, pp. 81–87.Google Scholar - 88.S.M. Thatte and J.A. Abraham, “Test Generation for Microprocessors,”
*IEEE Transactions on Computers*, vol. C-29, pp. 429–441, 1980.Google Scholar - 89.K. To, “Fault Folding for Irredundant and Redundant Combinational Circuits,”
*IEEE Transactions on Computers*, vol. C-22, no. 11, pp. 1008–1015, November 1973.Google Scholar - 90.B. Underwood, W.O. Law, S. Kang and H. Konuk, “Fastpath: A Path-delay Test Generator for Standard Scan Designs,”
*Proceedings of International Test Conference*, 1994, pp. 154–163.Google Scholar - 91.P. Varma, “On Path Delay testing in a Standard Scan Environment,”
*Proceedings of International Test Conference*, 1994, pp. 164–173.Google Scholar - 92.H.T. Vierhaus, W. Meyer and U. Glaser, “CMOS Bridges and Resistive Faults: IDDQ versus Delay Effects,”
*Proceedings of International Test Conference*, 1993, pp. 83–91.Google Scholar - 93.SH. Walker and S.W. Director, “VLASIC: A Catastrophic Fault Yield Simulator Integrated Circuits,”
*IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol*. CAD-5, pp. 541–556, October 1986.Google Scholar - 94.H. Walker, “VLASIC System User Manual Release 1.3,” SRC-CMU Research Center for Computer Aided Design, Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213.Google Scholar
- 95.R.L. Wadsack, “Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits,”
*Bell Systems Technical Journal, vol*. 57, no. 5, pp. 1449–1474, May-June 1978.Google Scholar - 96.T.W. Williams and K.P. Parker, “Design for Testability-A Survey,”
*Proceedings of the IEEE, vol*. 71, no. 1, pp. 98–113, January 1983.CrossRefGoogle Scholar - 97.B.W. Woodhall, B.D. Newman and A.G. Sammuli, “Empirical Results on Undetected CMOS Stuck-Open Failures,”
*Proceedings of International Test Conference*, 1987, pp. 166–170.Google Scholar

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