Nyquist-rate Converters: An Overview

  • Roberto Rivoir
Chapter

Abstract

Digital-to-analog and analog-to-digital converters are among the most important technology enablers for integrated circuits for communication applications. From a theoretical point of view, and in order to better study the different architectures, it is convenient to consider data converters as stand-alone IP (Intellectual Property) building blocks, and classify them according to the most important principles of operation. This leads us, for the sake of simplicity, and as it has been done in the current textbook, to define two main categories: Nyquist-rate and oversampled converters. This extreme simplification needs, however, some clarifications, that will be carried out in the paragraph dedicated to the converters architectures. Moreover, the “stand-alone IP-block” assumption should not lead to misleading interpretations, since in practical applications it is highly improbable to find spare ADCs or DACs used as stand-alone cells, to implement self-consistent functions. On the contrary, and especially in Systems-On-Chips (SOCs), ADCs and DACs are the core elements of much more highly integrated functions where, around the key operation of converting data from the analog (digital) domain to the digital (analog) domain, a number of other vital operations are implemented as well: i) integrate those building blocks that are indispensable for the converter to work properly (bandgap references, current references, reference buffers), ii) interface it to the external world (input buffers, programmable gain amplifiers, output buffers, power amplifiers, line drivers), iii) ensure proper conditions to reach a target performance (dc-dc converters, high PSRR voltage regulators, low jitter phase-locked loops), iv) provide a number of additional features to complete the functionality of the overall data conversion channel (antialiasing, reconstruction filtering, analog and/or digital channel filtering, serial/parallel I/O ports, offset compensation, overflow detection, power-up-down management, thermal protection, ...), and finally, sometimes neglected but extremely important, v) add that hardware overhead which allows a complete and cost effective testability of the system (SCAN test, BIST analog,...). Given a specific application, which determines consequently a specification for the whole data conversion system in terms of static and dynamic parameters (power supply, current consumption, power supply rejection ratio, integral and differential non-linearity, signal-to-noise ratio, total-harmonic distortion,...), the converter of choice will fall within a restricted number of architectures: oversampled or Nyquist rate, and in the last case slow speed, very high resolution (dual ramp, incremental), or medium speed, n-clock cycles (algorithmic, successive approximation), or finally very high speed, 1–2 clock cycles converters (pipeline, two-step flash, full flash, folding). Usually the data converter represents the most difficult building block to be developed, and the key knowledge of the designer concerning one of its possible architectures, determines not only the choice of the converter itself, but also the development of all remaining auxiliary functions around it. The specification of the data conversion channel directly translates into the one of the converter, and the auxiliary blocks have to be properly sized, in order to guarantee and preserve the full performance. The example of Fig. 1.1 can help to gain a more in depth understanding of the subject.

Keywords

Clock Cycle Data Converter Power Supply Rejection Ratio Full Scale Range Residue Amplifier 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    B. H. Leung, R. Neff, P. R. Gray, R. W. Brodersen, “Area-efficient multichannel oversampled PCM voice-band coder”, IEEE JSSC, vol. 23, No. 6, December 1988, pp. 1351–1357.Google Scholar
  2. [2]
    V. Friedman, D. M. Brinthaupt, D. P. Chen, T. W. Deppa, J. P. Elward, E. M. Fields, J. W. Scott, T. R. Viswanathan, “A dual-channel voice-band PCM codec using S? modulation technique”, IEEE JSSC, vol. 24, No. 2, April 1989, pp. 311–317.Google Scholar
  3. [3]
    G. Nicollini, S. Pernici, P. Confalonieri, C. Crippa, A. Nagari, S. Mariani, A. Calloni, M. Moioli, C. Dallavalle, “A high-performance analog frontend 14-bit codec for 2.7V digital cellular phones”, IEEE JSSC, Vol. 33, No. 8, August 1998, pp. 1158–1167.Google Scholar
  4. [4]
    F. Carassa, “Comunicazioni elettriche”, (tr. Electrical communications) Boringhieri, Italy, 1983, pp. 101-111Google Scholar
  5. [5]
    L. Calandrino, G. Immovilli, “Sistemi di modulazione per trasmissioni numeriche” (tr. Modulation systems for numerical transmissions), Patron, Italy, 1983, pp. 26-34Google Scholar
  6. [6]
    A. Hairapetian, “An 81-MHz IF receiver in CMOS”, IEEE JSSC Vol. 31, No. 12, December 1996, pp. 1981–1986.Google Scholar
  7. [7]
    J. Robert, G. C. Themes, V. Valencic, R. Dessoulavy, P. Deval, “A 16-bit low voltage CMOS A/D converter”, IEEE JSSC, Vol 22, April 1987, pp. 157–163.Google Scholar
  8. [8]
    J. Robert, P. Deval, “A second-order high resolution incremental A/D converter with offset and charge injection compensation”, IEEE JSSC, Vol. 23, June 1988, pp. 736–741.Google Scholar
  9. [9]
    R. Harjani, T. A. Lee, “FRC: a method for extending the resolution of Nyquist rate converters using oversampling”, IEEE Tansactions on Circuits and Systems — II, Vol. 45, No.4, April 1998, pp. 482–494.CrossRefGoogle Scholar
  10. [10]
    J. Yuan, C. Svensson, “A 10-bit 5-MS/s Successive Approximation ADC cell used in a 70-MS/s ADC array in 1.2-um CMOS”, IEEE JSSC, Vol. 29, No. 8, August 1994, pp. 866–872.Google Scholar
  11. [11]
    S. Y. Chin, C. Y. Wu, “A CMOS ratio independent and gain insensitive algorithmic analog-to-digital converter”, IEEE JSSC, Vol. 31, No. 8, August 1996, pp. 1201–1207.Google Scholar
  12. [12]
    H. S. Lee, “A 12-bit 600ks/s digitally self-calibrated pipelined algorithmic ADC”, IEEE JSSC, Vol. 29, No. 4, April 1994, pp. 509–515.Google Scholar
  13. [13]
    M. Yotsuyanagi, T. Etoh, K. Hirata, “A 10-bit 50-MHz pipelined CMOS A/D converter with S/H”, IEEE JSSC, Vol. 28, No. 3, March 1993, pp. 292–300.Google Scholar
  14. [14]
    B. Nauta, A. G. W. Venes, “A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter”, IEEE JSSC, Vol. 30, No. 12, December 1995, pp. 1302–1308.Google Scholar
  15. [15]
    M. P. Flynn, D. J. Allstot, “CMOS folding A/D converters with current mode interpolation”, IEEE JSSC, Vol. 31, No. 9, September 1996, pp. 1248–1257.Google Scholar
  16. [16]
    A. G. W. Venes, R. J. van de Plassche, “An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing”, IEEE JSSC, Vol. 31, No. 12, December 1996, pp. 1846–1853.Google Scholar
  17. [17]
    R. Rivoir, F. Maloberti, G. Torelli, “Digital to analog converter with dual resistor string”, US Patent No. 08/730,592Google Scholar

Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Roberto Rivoir

There are no affiliations available

Personalised recommendations