Modeling and Characterization of IC Interconnects and Packagings for the Signal Integrity Verification of High-Performance VLSI Circuits

  • Yungseon Eo
Part of the Network Theory and Applications book series (NETA, volume 8)

Abstract

Today’s state of the art VLSI circuits, microwave integrated circuits, and next generation VLSI or ULSI circuit designs face new challenging problems, that is, signal integrity problems. With the advent of deep submicron semiconductor processing technology, there has been rapid development of IC with integration of more than several hundred million transistors. These VLSI circuits will be operated with clock frequencies greater than several GHz. However, such an increase of integration level and speed raises the risk of poor noise margins and timing malfunctions during circuit operations. Therefore, when designing high performance VLSI circuits, very accurate design methodologies are required.

Keywords

Transmission Line VLSI Circuit Spice Simulation Crosstalk Noise Switching Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    R. J. Antinone and Gerald W. Brown, “The modeling of Resistive Interconnects for Intergrated Circuits,? IEEE Journal of Solid–State Circuits, vol SC–18, pp. 200–2–3, Apr. 1983.Google Scholar
  2. [2]
    T. Sakurai and K, Tamaru, “Simlpe Formula for Two-and Three- Dimensional Capacitances,” IEEE Trans. Electron Device, vol. ED-30, No. 2, pp. 183–185, Feb. 1983.CrossRefGoogle Scholar
  3. [3]
    T. Sakurai, “Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI,” IEEE Trans. ED., vol. 40, No. 1, pp. 118–124, Jan. 1993.MathSciNetCrossRefGoogle Scholar
  4. [4]
    W. C. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” Journal of Applied Physics, vol. 19, pp. 55–63, Jan. 1948.CrossRefGoogle Scholar
  5. [5]
    J. Rubinstein, P. Penfield, Jr., and M. Horowitz, “Signal Delay in RC Tree Networks,” IEEE Trans. CAD., vol. CAD-2, No. 3, pp. 202–211, July 1983.Google Scholar
  6. [6]
    H. R. Kaupp, “Waveform Degradation in VLSI Interconnections,” IEEE JSSC, vol. 24, pp. 1150–1153. Aug. 1989.Google Scholar
  7. [7]
    A. Deng and Y. Shiau, “Generic Linear RC Delay Modeling for Digital CMOS Circuits,? IEEE Trans. CAD., vol. 9, No. 4, pp. 367–376. Apr. 1990.CrossRefGoogle Scholar
  8. [8]
    T. Sakurai, “Approximation of Wiring Delay in MOSFET LSI,” IEEE JSSC., vol. SC-18, No. 4, pp. 418–426, Aug. 1983.Google Scholar
  9. [9]
    A. B. Kahng and S. Muddu, “An Analytical Model for RLC Interconnects,? IEEE Trans. CAD., Vol. 16, No. 12, pp. 1507–1514, Dec. 1997.CrossRefGoogle Scholar
  10. [10]
    Y. Massoud et al.,- “Layout Techniques for Minimizing On-Chip Interconnect Self Inductance? in Proc., ACM/IEEE Design Automation Conf., 1998, pp. 566–571.Google Scholar
  11. [11]
    B. Krauter and S. Mehrotra, “Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysisin Proc., ACM,? IEEE Design Automation Conf., 1998, pp. 303–308.Google Scholar
  12. [12]
    Y. I. Ismail, E. G. Friedman, and J. L. Neves, “Figure of Merit to Characterize the Importance of On-Chip Inductance,” in Proc., ACM/IEEE Design Automation Conf, 1998, pp. 560–565.Google Scholar
  13. [13]
    S. Lin and E. Kuh, “Transient Simulation of Lossy Interconnects Based on the Recursive Convolution Formulation,” IEEE Trans. CAS, vol. 39, pp. 879–892, Nov. 1992.MATHCrossRefGoogle Scholar
  14. [14]
    L. T. Pillage and R. A. Roller, “Asymptotic Waveform Evaluation for Timing Analysis,? IEEE Trans. CAD, vol. 9, No. 4, pp. 352–368, Apr. 1990.CrossRefGoogle Scholar
  15. [15]
    T. S. Blazeck and R. Mittra, “Transient Analysis of Lossy Multiconduc-tor Transmission Lines in Nonlinear Circuits,? IEEE Trans. CPMT., vol. 14, no. 3, pp. 618–627, Sep. 1991.Google Scholar
  16. [16]
    Y. Eo and W. R. Eisenstadt, “High-Speed VLSI Interconnect Modeling Based on S-Parameter Measurements,? IEEE Trans. CPMT., vol. 16, No. 5, pp. 555–562, Aug. 1993.Google Scholar
  17. [17]
    Y. Eo and W. R. Eisenstadt, “Simulation and Measurements of Picosecond Signal Transients, Propagation, and Crosstalk on Lossy VLSI Interconnect,? IEEE CPMT. Part A, vol 18, No. 1, pp. 215–225, Mar. 1995.Google Scholar
  18. [18]
    H. Guckel et al., “A parallel-Plate Waveguide Approach to Microminiaturized, Planar Transmission Lines for Integrated Circuits,? IEEE Trans. MTT., vol. 15, pp. 468–476, Aug. 1967.CrossRefGoogle Scholar
  19. [19]
    H. Hasegawa, M. Furukawa, and H. Yanai, “Properities of Microstrip Line on Si-Si0 System,? IEEE Trans. MTT, vol. MTT-19, pp. 869–881, Nov. 1971.Google Scholar
  20. [20]
    R. Sorrentino, G. Leuzzi, and A. Slbermann, “Characteristics of Metal-Insulator-Semiconductor Coplanar Waveguides for Monolithic Microwave Circuits,” IEEE Trans. MTT, vol. 32, no. 4, pp. 410–416, Apr. 1984.CrossRefGoogle Scholar
  21. [21]
    Y. Fukuoka. Y. Shih, and T. Itoh, ?Analysis of Slow-Wave Coplanar Waveguide for Monolithic Integrated Circuits,“ IEEE Trans. MTT., vol. 31, No. 7, pp. 567–573, Jul. 1983.CrossRefGoogle Scholar
  22. [22]
    T. Shibata and E. Sano, Characterization of MIS Structure Coplanar Transmission Lines for Investigation of Signal Propagation in Integrated Circuits,? IEEE Trans. MTT., vol. 38, No. 7, pp. 881–890, Jul. 1990.CrossRefGoogle Scholar
  23. [23]
    E. Groteluschen, L. S. Dutta, and S, Zaage, “Quasi-Analytical Analysis of the Broadband Properties of Multiconductor Transmission Lines on Semiconducting Substrates,” IEEE Trans. CPMT-B, vol. 17, No. 3, pp. 376–382, Aug. 1994.Google Scholar
  24. [24]
    W. R. Eisenstadt and Y. Eo, “S-Parameter-Based IC Interconnect Transmission Line Characterization,? IEEE Trans. CPMT., vol. 15, No. 4, pp. 483–490, Aug. 1992.Google Scholar
  25. [25]
    C. C. Courtney, “Time-Domain Measurement of the Electromagnetic Properties of Materials,? IEEE Trans. MTT., vol., 46, No. 5, pp. 517–522, May 1998.CrossRefGoogle Scholar
  26. [26]
    J. Wee et al., “Modeling the Substrate Effect in Interconnect Line Char-acterisitics of High-Speed VLSI Circuits,” IEEE Trans. MTT., vol., 46, No. 5, pp. 1436–1443, Oct. 1998.Google Scholar
  27. [27]
    D. F. Williams, U. Arz, and H. Grabinski, “Accurate Characteristic Impedance Measurement on Silicon,” IEEE MTT-S Int. Microwave Symposium Digest, 1998, pp. 1917–1920.Google Scholar
  28. [28]
    J. E. Schutt-Aine, R. Mittra, “Scattering Parameter Transient Analysis of Transmission Lines Loaded with Nonliear Terminations,” IEEE Trans. MTT., vol. 36, No. 3, pp. 529–536, Mar. 1988.CrossRefGoogle Scholar
  29. [29]
    R. Achar, M. Nakhla, and E. Ahmed, “Nonlinear Transient Simulation of Embedded Subnetworks Characterized by S-parameters Using Complex Frequency Hopping,” IEEE MTT-S Int. Microwave Symposium Digest, 1998, pp. 267–270.Google Scholar
  30. [30]
    A. Verschueren et al., “Identifying S-Parameter Models in the Laplace Domain for High Frequency Multiport Linear Network,” IEEE MTT-S Int. Microwave Symposium Digest, 1998, pp. 25–28.Google Scholar
  31. [31]
    R J. Restle, K. Al Jenkins, A. Deutch, and R W. Cook, “Measurement and Modeling of On-Chip Transmission Line Effects in a 400 MHz Microprocessor,” IEEE JSSC., vol. 33, No. 4, pp. 662–665, Apr. 1998.Google Scholar
  32. [32]
    D. W. Bailey and B. J. Benschneider, “Clocking Design and Analysis for a 600-MHz Alpha Microprocessor,” IEEE JSSC, vol. 33, No. 11, pp. 1627–1633, Nov. 1998.Google Scholar
  33. [33]
    J. -H. Chern, J. Huang, L. Arledge, R -C. Li, and R Yang, “Multilevel metal capacitance models for CAD design synthesis systems,” IEEE Electron Device Letters, vol. 13, no. 1, pp. 32–34, Jan. 1992.CrossRefGoogle Scholar
  34. [34]
    J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H. -C. Yen, “Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology,” in Proc. 34th Design Automation Conf., 1997, pp. 627–632.Google Scholar
  35. [35]
    N. D. Arora, K. V. Raol, R. Schumann, and L. M. Richardson, “Modeling and extraction of interconnect capacitance for multilayer VLSI circuits,? IEEE Trans. Computer-Aided Design, vol. 15, no. 1, pp. 58–67, Jan. 1996.CrossRefGoogle Scholar
  36. [36]
    U. Choudhury and A. Sangiovanni-Vincentelli, “Automatic generation of analytical models for interconnect capacitances,” IEEE Trans. Computer-Aided Design, vol. 14, no. 4, pp. 470–480, Apr. 1995.CrossRefGoogle Scholar
  37. [37]
    W. T. Weeks, Calculation of coefficients of capacitance of multiconduc-tor transmission lines in the presence of a dielectric interface IEEE Trans. Microwave Theory Tech., vol. MTT-18, no. 1, pp. 35–43, Jan. 1970.CrossRefGoogle Scholar
  38. [38]
    A. E. Ruehli and P. A. Brennan, “Capacitance Models for Intergated Circuit Matalization Wires,” IEEE Trans IEEE Journal of Solid State Circuit, vol. SC-10 No. 6, pp. 530–536, Dec., 1975.Google Scholar
  39. [39]
    E. Bogatin and Gaga Test Labs, Microwave Basic’s Short Course, CA, 1992.Google Scholar
  40. [40]
    P. R. Gray and R. G. Meyer, Analysis and Design of Analog Intergrated Circuits, John Wiley and Sons, Inc., New York, 1984.Google Scholar
  41. [41]
    C. Wei, R. H. Harrington, J. R. Mautz, and T. K. Sarkar, “Multi-conductor transmission Lines in Multilayered Dielectric Media,” IEEE Trans. MTT vol. 32, no. 4, pp. 439–450, Apr., 1984.Google Scholar
  42. [42]
    J. S. Ko, B. K. Kim, and K. Lee, “Simple modeling of coplanar waveguide on thick dielectric over lossy substrate,? IEEE Trans, on EC, vol. 44, no. 5, pp. 856–861, May 1997.Google Scholar
  43. [43]
    Y. R. Kwon, V. M. Hietala, and K. S. Champlin, “Quasi-TEM analysis of slow-wave mode propagation on coplanar micro structure MIS transmission lines,” IEEE Trans. Microwave Theory and Tech., vol. 35, no. 6, pp. 545–551, June 1987.CrossRefGoogle Scholar
  44. [44]
    M. Wo Beattie and L. T. Pileggi, “IC analyses including extracted inductance models,” Proc. 36th ACM/IEEE Design Automation Conf., pp. 915–920, 1999.Google Scholar
  45. [45]
    S. V. Morton, “On-chip inductance issues in multiconductor systems,? Proc. 36th ACM/IEEE Design Automation Conf., pp. 921–926, 1999.Google Scholar
  46. [46]
    J. A. Davis and J, D. Meindl, “Compact distributed RLC models for multilevel interconnect networks,? 1999 Symposium on VLSI Circuits Digest of Technical Papers, 1999.Google Scholar
  47. [47]
    W. Jin, S. Yoon, Y. Eo, and J. Kim, “Experimental Characterization and Modeling of Transmission Line Effects for High-Speed VLSI Circuit Interconnects,” IEICE Trans, on Electronics, vol E83-C, no. 5, pp’. 728–735, May 2000.Google Scholar
  48. [48]
    Y. Ikawa, W. R. Eisenstadt, and R. W. Dutton, “Modeling of High- Speed, Large-Signal Transistor Switching Transients from S-Parameter Measurements,” IEEE Trans. ED., vol-ED 29, no. 4, pp. 669–675. 1982.CrossRefGoogle Scholar
  49. [49]
    J. L. Wyatt, Jr., “Signal Delay in RC Mesh Networks,” IEEE Trans. CAS, vol. CAS-32, pp. 507–510, May 1985.Google Scholar
  50. [50]
    M. Hatamian, L. A. Hornak, E. E. Little, S. K. Tewksbury, and P. Fran-zon, “Fundamental Interconnect Issues,” ATandT Technical Journal, vol. 66, Issue 4, pp. 13–30, Jul. 1987.Google Scholar
  51. [51]
    A. N. Saxena, “Interconnect for the J 90s: Aluminium-Based Multilevel Interconnects and Future Directions,? IEDM 1992 Short Course: Interconnect for the ‘80s, San Jose, CA, 1992.Google Scholar
  52. [52]
    A. R. Djordjevic, T. K. Sarkar, and R. F. Harrington, “Time Domain Response of Multiconductor Transmission Lines, ” Proceedings of IEEE, vol. 75, No. 6, pp. 743–764, Jun. 1987.CrossRefGoogle Scholar
  53. [53]
    G. Ghione, I. Maio, and G. Vecchi, “Modeling of Multiconductor Buses and Analysis of Crosstalk, Propagation Delay and Pulse Distortion in High-Speed GaAs Logic Circuits,” IEEE Trans. MTT., vol. 37, No. 3, pp. 445–456, Mar. 1989.CrossRefGoogle Scholar
  54. [54]
    D. Winklestein, M. B. Steer and R. Pomerleau, “Simulation of Arbitrary Transmission Line Networks with Nonlinear Terminations” IEEE Trans. CAS., vol. 38, No. 4, pp. 418–422, Apr. 1991.CrossRefGoogle Scholar
  55. [55]
    H. You and M. Soma, “Crosstalk Analysis of Interconnect Lines and Packages in High Speed Integrated Circuits” IEEE Trans. CAS., vol. 37, No. 8, pp. 1019–1026, Aug. 1990.MathSciNetCrossRefGoogle Scholar
  56. [56]
    D. Nayak, et al., “Calculation of Electrical Prameters of a Thin-Film Multichip Package” IEEE Trans. CHMT., vol. 12, No. 2, pp. 303–369, Jun. 1989.MathSciNetGoogle Scholar
  57. [57]
    J. C. Isaacs, Jr. and N. A. Strakhov,? Crosstalk in Uniformly Coupled Lossy Transmission Line“ Bell Syst. Tech. J., vol. 52, No.l, pp. 101–111, Jan. 1973.Google Scholar
  58. [58]
    M. Shoji, “CMOS Digital Circuit Technology, Englewood Cliffs, NJ: Prentice- Hall, 1988.Google Scholar
  59. [59]
    F. Dartu and L. T. Pileggi, “Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling,” in Proc. 34th Design Automation Conf, pp. 46–51, Jun. 1997.Google Scholar
  60. [60]
    C. R Yuan and T. N. Trick, “A Simple Formula for the Estimation of the Capacitance of Two-Dimensional Interconnects in VLSI Circuits,” IEEE Electron Device Letter, vol. EDL-3, No. 12, pp. 391–393, Dec. 1982.CrossRefGoogle Scholar
  61. [61]
    R. Evans and M. Tsuk, “Modeling and Measurement of a High- Performance Computer Power Distribution System,? IEEE Trans. CPMT-Part B. vol. 17, No. 4, pp. 467–471, Nov. 1994.Google Scholar
  62. [62]
    A. Vaidyanath, B. Thoroddsen, and J. L. Prince, “Effect of CMOS Driver Loading Conditions on Simultaneous Switching Noise,” IEEE Trans. CPMT, vol. 17, pp. 1724–1728, Nov. 1991.Google Scholar
  63. [63]
    S. R. Vemuru, “Accurate Simultaneous Switching Noise Estimation Including Velocity-Saturation Effect,” IEEE Trans. CPMT-PAPT B, vol., 19, No. 2, pp. 344–349. May 1996.Google Scholar
  64. [64]
    R. Senthinathan et al., “Electrical Package Requirements for Low- Voltage Ics-3.3V High-Performance CMOS Devices as a Case Study,” IEEE Trans. CPMT-Part B, vol. 17, No. 4, pp. 493–503, Nov. 1994.Google Scholar
  65. [65]
    A. J. Rainal, “Computing Inductive Noise of CMOS Drivers,” IEEE Trans. CPMT.- Part B, vol. 19, No. 4, pp. 789–802, Nov. 1996.Google Scholar
  66. [66]
    K. Bathey, M. Swaminathan, L. D. Smith, and T. J. Cockerill, “Noise Computation in Single Chip Packages,” IEEE Trans. CPMT-Part B, vol. 19, No. 2, pp. 350–360, May 1996.Google Scholar
  67. [67]
    J.-G. Yook et al., “Computation of Switching Noise in Printed Circuit Boards,” IEEE Trans. CPMT.-Part A, vol. 20, No. 1, pp. 64–75, Mar. 1997.Google Scholar
  68. [68]
    T. J. Gabara et al, “Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers,” IEEE JSSC, vol. 32, No. 3, pp. 407–418, Mar. 1997.Google Scholar
  69. [69]
    H. I. Hanafi et al., “Design and Characterization of a CMOS Off- Chip Driver/Receiver with Reduced Power-Supply Disturbance,” IEEE JSSC., vol. 27, No. 5, pp. 783–791, May 1992.Google Scholar
  70. [70]
    R. Senthinathan and J. L. Prince, “Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise,” IEEE JSSC. vol. 28, No. 12, pp. 1383–1388, Dec. 1993.Google Scholar
  71. [71]
    Y. Yang and J. R. Brews, “Design Trade-Offs for the Last Stage of an Unregulated, Long-Channel CMOS Off-Chip Driver with Simultaneous Switching Noise and Switching Time Consideration,” IEEE Trans. CPMT-PART B, vol. 19, No. 3, pp. 481–486, Aug. 1996.Google Scholar
  72. [72]
    Y. Yang and J. R. Brews, “Design for Velocity Saturated, Short-Channel CMOS Drivers with Simultaneous Switching Noise and Switching Time Considerations,” IEEE JSSC. vol., 31 No. 9, pp. 1357–1360, Sep. 1996.Google Scholar
  73. [73]
    D. A. Seeker and J. L. Prince, “Effects and Modeling of Simultaneous Switching Noise for BiCMOS OFF-Chip Drivers,” IEEE CPMT.-Part B, vol, 19, No. 3 pp. 473–480, Aug. 1996.Google Scholar
  74. [74]
    Y. Yang and J. R. Brews, “Guidelines for High-Performance Electronic Package Interconnections-Approach for Strong Coupling,? IEEE Trans. CPMT.-Part B, vol. 19, No. 2, pp. 372–381, May 1996.Google Scholar
  75. [75]
    T. Sakurai and A. Newton, “Alpha-Power Law MOSFET Model and Its Application to CMOS Inverter Delay and Other Formulas,” IEEE JSSC, vol. 25, pp. 584–549, Apr. 1990.Google Scholar
  76. [76]
    M. E. Van Valkenburg, Network Analysis, Reading, NY: Prentice Hall, 1974, Ch.6, pp.139–163.Google Scholar
  77. [77]
    P. Larsson, “Resonance and Damping in CMOS Circuits with On- Chip Decoupling Capacitance,” IEEE Trans. Circuits and System-I: Fundamental Theory and Applications, vol. 45, No. 8, pp. 849–858, Aug. 1988.CrossRefGoogle Scholar
  78. [78]
    Y. Eo, W. R. Eisenstadt, J. Y. Jeong, and 0-. K. Kwon, “A New On- Chip Interconnect Crosstalk Model and Experimental Verification for CMOS VLSI Circuit Design,” IEEE Trans, on Electron Devices, vol. 47, no. 1, pp. 129–140, Jan. 2000.CrossRefGoogle Scholar
  79. [79]
    Y. Eo, W. R. Eisenstadt, J. Y. Jeong, and 0-. K. Kwon, “New Simultaneous Switching Noise Analysis and Modeling for High-Speed and High-Density CMOS IC Package Design,” IEEE Trans, on Advanced Packaging, vol. 23, no. 2, pp. 303–312, May 2000.CrossRefGoogle Scholar
  80. [80]
    Y. Eo, W. R. Eisenstadt, and J. Shim, S-Parameter-Measurement- Based High-Speed Signal Transient Characterization of VLSI Interconnects,“ IEEE Trans, on Advanced Packaging, vol. 23, no. 3, pp. 470–479, Aug. 2000.Google Scholar
  81. [81]
    MEDICI User’s Manual,“ TMA Corp, Sunnyvale, CA.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • Yungseon Eo
    • 1
  1. 1.Department of Electrical and Computer EngineeringHanyang UniversityAnsan, Kyungki-DoSouth Korea

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