Techniques for Timing-Driven Routing

  • John Lillis
Part of the Network Theory and Applications book series (NETA, volume 8)

Abstract

With every new generation of fabrication technology for VLSI we see an increased influence of interconnect on system performance. With device scaling interconnect parasitics become increasingly influential. Issues such as layer assignment, via resistance, wire-to-wire coupling capacitance, wire width and signal buffering now play major roles in determining signal delay.

Keywords

Priority Queue Path Delay Coupling Capacitance Source Vertex Delay Estimator 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    C. J. Alpert, A. Devgan, J. P. Fishburn, S. T. Quay, Interconnect Synthesis Without Wire Tapering, IEEE Transactions on Computer-Aided Design,Vol. 20, No. 1, Jan. 2001, pp. 90–104Google Scholar
  2. [2]
    C.-P. Chen, Y.-P. Chen, D.F. Wong, Optimal Wire-Sizing Formula under the Elmore Delay Model, Proc. Design Automation Conference, pp. 487-490, June 1996.Google Scholar
  3. [3]
    C.-K. Cheng, J. Lillis, S. Lin and N. Chang, Interconnect Analysis and Synthesis, (Wiley Interscience), 2000.Google Scholar
  4. [4]
    C. C. N. Chu and D. F. Wong. Closed Form Solution to Simultaneous Buffer Insertion/Sizing and Wire Sizing. Proc. Intl. Symp. on Physical Design, pp. 192–197, 1997.Google Scholar
  5. [5]
    T. H. Cormen, C. E. Leiserson, R. L. Rivest, Introduction to Algorithms, (McGraw Hill), 1989.Google Scholar
  6. [6]
    W.C. Elmore, The transient response of damped linear networks with particular regard to wide-band amplifiers, Journal of Applied Physics, 19 (1): pp. 55–63, Jan. 1948.CrossRefGoogle Scholar
  7. [7]
    J.P. Fishburn, private communication (2000).Google Scholar
  8. [8]
    J.P. Fishburn, C.A. Schevon, Shaping a distributed-RC line to minimize Elmore delay, IEEE Trans. Circuits Syst. I, vol. 42, pp. 1020–1022.Google Scholar
  9. [9]
    R. Gupta, B. Tutuianu and L. Pileggi, The Elmore Delay as a Bound for RC Trees with Generalized Input Signals, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 95–104, January 1997.Google Scholar
  10. [10]
    P.E. Hart, N.J. Nilsson, B. Raphael, A Formal Basis for the Heuristic Determination of Minimum Cost Paths, IEEE Trans. Syst. Cybern., vol. SCC-4, pp. 100–107, July 1968.Google Scholar
  11. [11]
    J. Hu and S. S. Sapatnekar, Algorithms for Non-Hanan-based Optimization for VLSI Interconnect under a Higher Order AWE Model, IEEE Transactions on CAD, Vol. 19, No. 4, pp. 446–458, April 2000.Google Scholar
  12. [12]
    S.-W. Hur, A. Jagannathan, J. Lillis, Timing-Driven Maze Routing, IEEE Trans. on CAD, vol. 19, no. 2, pp. 234–241.Google Scholar
  13. [13]
    A. Jagannathan, S.-W. Hur, J. Lillis, A Fast Algorithm for Context-Aware Buffer Insertion, Proc. Design Automation Conference, pp. 368–373, June 2000.Google Scholar
  14. [14]
    H.C. Joksch, The Shortest Route Problem with Constraints J. Math Anal. Appl., 14, pp. 191–197, 1966.MathSciNetMATHCrossRefGoogle Scholar
  15. [15]
    M. Lai, D.F. Wong, Maze Routing with Buffer Insertion and Wiresizing, Proc. Design Automation Conference, pp. 374–378, June 2000.Google Scholar
  16. [16]
    E. Lawler, Combinatorial Optimization, Networks and Matroids, (Hold, Rinehart, Winston), pp. 94–97, 1976.Google Scholar
  17. [17]
    J. Lillis, C.-K. Cheng, T.-T. Y. Lin, Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model, IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 437–447, 1996.CrossRefGoogle Scholar
  18. [18]
    J. Qian, S. Pullela and L.T. Pillage, Modeling the “Effective Capacitance” of RC Interconnect, IEEE Transactions on Computer-Aided Design, pp. 1526–1535, December 1994.Google Scholar
  19. [19]
    J. Lillis, P. Buch, Table-Lookup Methods for Improved Performance Driven Routing, Proc. Design Automation Conference, pp. 368–377, June 1998.Google Scholar
  20. [20]
    H. Zhou, D.F. Wong, I.-M. Liu, A. Aziz, Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations, Proc. Design Automation Conference, pp. 96–99, June 1999.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • John Lillis
    • 1
  1. 1.Department of Computer ScienceUniversity of IllinoisChicagoUSA

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