Modern Standard-cell Placement Techniques

  • Xiaojian Yang
  • Elaheh Bozorgzadeh
  • Majid Sarrafzadeh
  • Maogang Wang
Part of the Network Theory and Applications book series (NETA, volume 8)

Abstract

Placement is a classical problem in VLSI physical design. A lot of effective placement tools have been proposed in the last twenty years [1, 2, 3, 4, 5]. Previous work on the placement problem falls into two classes: constructive and iterative. It is generally believed that iterative approaches can produce better results than constructive approaches but are slower. The intense competition is driving the electronic design automation tools to finish designs in the shortest amount of time. When the circuit size gets larger and larger, quality degradation is expected for the flat iterative approaches. The multi-level hierarchical technique is regarded indispensable for solving today’s complex VLSI placement problem without sacrificing quality. Most recent placement tools [1, 3, 4, 5] employ hierarchical approaches, including top-down annealing approaches [3, 5] and recursive quadratic methods [1, 4].

Keywords

Hierarchical Level Hierarchical Placement Terminal Propagation Runtime Comparison Global Placement 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • Xiaojian Yang
    • 1
  • Elaheh Bozorgzadeh
    • 1
  • Majid Sarrafzadeh
    • 1
  • Maogang Wang
    • 2
  1. 1.Computer Science DepartmentUniversity of CaliforniaLos AngelesUSA
  2. 2.Simplex Solutions, Inc.SunnyvaleUSA

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