Interconnect Planning

  • Jason Cong
Part of the Network Theory and Applications book series (NETA, volume 8)

Abstract

The driving force behind the spectacular advancement of the integrated circuit technology in the past thirty years has been the exponential scaling of the transistor feature size, i.e., the minimum dimension of a transistor. It has been following the Moore’s Law [1] at the rate of a factor of 0.7 reduction every three years. It is expected that such exponential scaling will continue for at least another 10 to 12 years as projected in the 1997 National Technology Roadmap for Semiconductors (NTRS’97) [2] shown in Table 1.1

Keywords

Feasible Region Delay Constraint Wire Width Global Interconnect Exponential Scaling 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • Jason Cong
    • 1
  1. 1.Department of Computer ScienceUniversity of CaliforniaLos AngelesUSA

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