Implementation Using Hardware Multiplier(s) and Adder(s)
If an application’s performance requirements cannot be met by a programmable DSP, one option is to use multiple processors. A more area-delay-power efficient solution is to build a processor that is customized for the application. Such a solution typical offers limited capabilities and limited programmability. However, if these are adequate for the application and are of lesser importance than the area-delay-power requirements, such a dedicated solution is the preferred option. The problem of hardware realization from an algorithmic description of an application, has been extensively discussed in the literature. Many silicon-compilers such as HYPER , CATHEDRAL  and MARS  address this problem of high level synthesis. The domain of high level transformations has also been well studied and many such techniques have been presented in the literature [14, 60]. The problem of high level synthesis for low power has been addressed in  and the technique of using multiple supply voltages for minimizing energy has been discussed in . This chapter first presents architectural transforms from high level synthesis domain and evaluates the applicability of some of these techniques in the context of FIR filters (weighted-sum computation in general). It then presents a detailed analysis of multirate architectures as a transform that reduces the computational complexity of FIR filtering, thereby providing performance/power advantage.
KeywordsPower Dissipation High Level Synthesis Data Flow Graph Signal Flow Graph Critical Path Delay
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