Fully Integrated CMOS Frequency Synthesizers for Wireless Communications

  • Bram De Muer
  • Michiel Steyaert

Abstract

This work presents a design strategy for fully integrated CMOS frequency synthesizers, using the DCS-1800 class I/II standard as driving application. The design of the loop filter is emphasized. The goal is to minimize the integrated capacitance while maintaining the required phase noise and dynamic performance by proper filter topology selection and optimization of the loop parameters. Based on these results, a type-II, fourth-order PLL frequency synthesizer is implemented in a standard 0.25μm CMOS technology, including a monolithic voltage controlled oscillator and a fully integrated loop filter. The measurements show full compliance with the DCS-1800 class I/II specifications, while the occupied area is only 2 × 2 mm2. To conclude, the influence of ∆∑ fractional-N division control on the performance of the PLL frequency synthesizer is discussed.

Keywords

Phase Noise Charge Pump Voltage Control Oscillator Loop Filter Frequency Synthesizer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2000

Authors and Affiliations

  • Bram De Muer
    • 1
  • Michiel Steyaert
    • 1
  1. 1.ESAT-MICASKatholieke Universiteit LeuvenHeverleeBelgium

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