Register Allocation for DSP Data Paths
This chapter deals with the register allocation problem in DSP code generation. Since DSP data paths typically show special-purpose registers, register allocation for such architectures has to be performed carefully in order to achieve high code quality. In particular, this holds if code is generated for data flow graphs, which are a widespread internal representation of program blocks. Such data flow graphs are composed of data flow trees, for which satisfactory code generation techniques have already been developed. In the following, we will extend this work by an algorithm that allocates registers for common subexpressions in data flow graphs, which can be considered as the interfaces between the data flow trees in the graph.
KeywordsBasic Block Data Path Tree Parsing Intermediate Representation Grammar Rule
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