1.2 Gb/s CML Transceiver with 1M CMOS ATM/SDH Processor in a BICMOS Monochip
A B-ISDN Mixed Signal Design combining very high speed 1.2GHz analog PLLs with high integration level 1Mtr. CMOS Processor is depicted. Architectural choices are presented emphasizing power reduction techniques to achieve 1.5W total consumption. Low noise design style is shown with less than 18ps rms jitter performance. The practical mixed design techniques applied to this chip are described as well as DFT strategy and measurements result.
KeywordsRegistered Trademark Architectural Choice Cell Processor Synchronous Digital Hierarchy Jitter Performance
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