Logic Optimization

  • Wolfgang Kunz
  • Dominik Stoffel
Part of the Frontiers in Electronic Testing book series (FRET, volume 9)

Abstract

Multi-level logic optimization figures prominently in the synthesis of very large integrated circuits. Sections 5.1 to 5.3 briefly review basic approaches in multilevel logic optimization. The main objective of this chapter is to demonstrate the intimate relationship between algorithmic concepts of test generation, the AND/OR reasoning of Chapters 3 and 4 and common notions of logic synthesis. Section 5.6 develops a new approach to multi-level logic optimization based on the methods presented in Chapters 3 and 4.

Keywords

Boolean Network Functional Decomposition Fault List Prime Implicants Logic Optimization 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1997

Authors and Affiliations

  • Wolfgang Kunz
    • 1
  • Dominik Stoffel
    • 1
  1. 1.University of PotsdamGermany

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