RISC and DSP Cores

  • Vasudev Bhaskaran
  • Konstantinos Konstantinides
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 334)

Abstract

As noted in the previous chapter, most video compression ICs utilize either a RISC or a DSP core as their central controller and processing unit. By RISC or DSP core we imply a standard programmable processor, without the I/O pads, buffers, and associated circuitry. These parts are replaced by custom circuits that interface to the rest of the architecture. The main goal in using a processing core is to take advantage of existing hardware and software resources (such as arithmetic processing units, memory, operating system support, and language compilers) and to minimize the design time of a more complex and dedicated IC. In this chapter we describe the basic architectures of a RISC core and a DSP core and some of their similarities and differences.

Keywords

Instruction Cache Operate System Support RISC Processor Texas Instrument Address Generation Unit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1995

Authors and Affiliations

  • Vasudev Bhaskaran
    • 1
  • Konstantinos Konstantinides
    • 1
  1. 1.Hewlett-Packard LaboratoriesUSA

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