Design Considerations for High-Speed Low-Power Low-Voltage CMOS Analog-to-Digital Converters
This paper describes architecture and circuit approaches for the design of high-speed, low-power, pipelined analog-to-digital converters in CMOS. The role of pipeline architectures in high--speed conversion is first discussed. Then a number of design issues related to power optimization in pipeline A/D converters are discussed, including power minimization in switched capacitor gain blocks operated on low supply voltages, implementation of transmission gates on low voltages, and capacitor scaling in pipelines. The application of these approaches is illustrated using results from an experimental 10-bit 20-MS/s pipeline A/D converter implemented in 1.2-μm CMOS technology that achieves a power dissipation of 35 mW at full speed operation.
KeywordsPower Dissipation Settling Time Operational Amplifier Parasitic Capacitance Charge Pump
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