Putting the Pieces Together

  • Douglas E. Ott
  • Thomas J. Wilderotter
Chapter

Abstract

Up to this point, the discussions have focussed on VHDL and logic synthesis design issues. This chapter discusses how to combine the various design entities and related pieces together into a complete ASIC, and how to generate VHDL test benches for simulation.

Keywords

Pulse Train Test Bench Design Entity VHDL Code Serial Data Stream 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1994

Authors and Affiliations

  • Douglas E. Ott
    • 1
  • Thomas J. Wilderotter
    • 1
  1. 1.ITT AvionicsUSA

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