Combinational Logic and Optimization
This chapter discusses the synthesis of purely combinational circuits, and how the logic optimization capabilities of synthesis tools can be used to control gate count and path delays through the logic. In the examples, the interaction of the ASIC library with the optimization tools will be illustrated along with the effect of the library’s rules for loading and wire delays.
KeywordsFull Adder Combinational Logic Combinational Circuit Logic Minimization Synthesis Tool
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