There are two types of nets in VLSI systems that need special attention in routing: Clock nets and Power/Ground nets. The chip performance is directly proportional to clock frequency. Clock nets need to be routed with great precision, since the actual length of the path of a net from its entry point to its terminals determines the maximum clock frequency on which a chip may operate. A clock router needs to take several factors into account, including the resistance and capacitance of the metal layers, the noise and cross talk in wires, and the type of load to be driven. In addition, the clock signal must arrive simultaneously at all functional units with little or no waveform distortion. Compared to clock routing, power and ground routing is relatively simple. However, due to the large amount of current that these nets carry, power and ground lines are wide. Concerns such as current density and the total area consumed make it necessary to develop special routers for power and ground nets. In this chapter, we will discuss the problems associated with clock, power and ground routing and present the basic routing algorithms for these special nets.
KeywordsClock Frequency Clock Signal Clock Period Gate Capacitance Specialize Route
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