Abstract

After completion of detailed routing, the layout is functionally complete. At this stage, the layout is ready to be used to fabricate a chip. However, due to non—optimality of placement and routing algorithms, some vacant space is present in the layout. In order to minimize the cost, improve performance and yield, layouts are reduced in size by removing the vacant space without altering the functionality of the layout. This operation of layout area minimization is called layout compaction.

Keywords

Grid Line Constraint Graph Connectivity Constraint Virtual Grid Layout Area 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1993

Authors and Affiliations

  • Naveed A. Sherwani
    • 1
  1. 1.Western Michigan UniversityUSA

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