This chapter describes the defect models used in our research. These models perform two functions. First, the models provide a geometrical abstraction of local defects. In other words, defects are modeled as geometrical modifications to the specified layout geometry. Second, the models describe how layout geometry combines to form circuit faults. This information can then be used in the fault analysis phase.
KeywordsIntegrate Circuit Defect Model Local Defect Defect Type Yield Simulation
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