This chapter reviews previous work in the area of yield simulation for the purpose of motivating the research we have undertaken. Most of the work to date has been in terms of generating analytic formulas that at best predict the number of circuit faults on a chip, are limited in that these formulas are only valid for a typical layout [Bertram 83, Glaser 77, Stapper 83a]. More accurate analyses have been done using a combination of analytic and Monte Carlo techniques [Stapper 80, Maly 85a]. Most Monte Carlo analysis has been oriented towards predicting yield for circuits with redundancy [Kung 84, York 85] or design rule optimization [Razdan 85].
KeywordsProbability Density Function Defect Density Defect Type Yield Simulation Poisson Statistic
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