Frontiers of Computing Systems Research pp 61-130 | Cite as

# The Limitations of Interconnections in Providing Communication Between an Array of Points

## Abstract

We present a comparative analysis of optical, normally conducting, re-peatered and superconducting interconnection performance in a very large scale digital computing environment. We derive tradeoff relations between delay, bandwidth and system size for each technology based on communication (wiring) volume and heat removal considerations and discuss their numerical and asymptotic properties. We show that the bisection-bandwidth and bisection-inverse delay products—which are appropriate measures of performance for communication limited applications—are bounded from above for normally conducting layouts, whereas they may be arbitrarily increased for repeatered, optical and superconducting layouts. The latter two are shown to suffer slower growth rate of signal delay with increasing system size in 3 dimensions than repeatered interconnections and thus offer the best performance. Based on the considerations of this paper, the comparison between optical and superconducting interconnections for same dimensional layouts reduces to a comparison of their respective communication energies.

## Keywords

Heat Removal Normal Conductor Optical Interconnection Connection Graph Increase System Size## List of Symbols

*a*system radius in grid units

- (
*area*) cross sectional area associated with each physical line

*B*bit repetition rate along each edge of connection graph

*c*vacuum velocity of light

*C*capacitance per unit length

*d*linear extent of a unit cell

*d*_{d}linear extent of an element

*d*_{trans}linear extent of a transducer

*e*Euclidean dimension of layout space

*E*energy associated with each transmitted bit of information

*f*(∙)functional form of connection flux distribution

*g*(∙)functional form of line length distribution

*h*height of dielectric

*H*bisection

*J*_{c}volume critical current density

*J*_{sc}surface critical current density

*k*number of graph edges per element

*K*number of wiring tracks per cell

*l*length of a line in real units

*L*inductance per unit length

*m*order of moment of line length distribution

*M*number of wiring layers

*n*fractal dimension of layout

*N*number of elements

*p*interConnectivity (Rent exponent) of layout

*Q*maximum amount of power we can remove per cross section

*r*length of a line in grid units

*̄r*average connection length in grid units

- <
*r*^{m}> *m*th moment of line length distribution*R*resistance per unit length

*R*_{d}drive impedance

*R*_{0}*C*_{0}intrinsic delay of repeating devices

*S*inverse of worst case signal delay

*S*_{ave}inverse of average signal delay

*t*height of conductor

*T*minimum temporal pulse width associated with each transmitted bit of information

*S*_{d}device imposed component of

*T**T*_{e}line imposed component of

*T**T*_{p}propagation delay along a line

*T*_{r}minimum pulse repetition interval along a line

*V*nominal logic voltage level

*w*width of conductor

- (
*width*) transverse linear extent associated with each physical line

*Z*_{0}characteristic impedance

*α*attenuation constant

*ϰ*number of parallel physical lines used to establish each graph edge

*δ*classical skin depth

*ε*permittivity of dielectric

*κ*coefficient for average connection length

*λ*optical wavelength

*λ*superconducting penetration depth

*μ*permeability of dielectric

*ρ*resistivity of conductor

*τ*worst case signal delay

*τ*_{ave}average signal delay

*υ*velocity of propagation

*ω*fundamental frequency component

*ξ*optimal number of repeater stages

*ζm, ζ’m, ζ”m*coefficients for the moments of line length distribution

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