Advertisement

The Limitations of Interconnections in Providing Communication Between an Array of Points

  • Haldun M. Ozaktas
  • Joseph W. Goodman
Part of the Frontiers of Computing Systems Research book series (FCSR, volume 2)

Abstract

We present a comparative analysis of optical, normally conducting, re-peatered and superconducting interconnection performance in a very large scale digital computing environment. We derive tradeoff relations between delay, bandwidth and system size for each technology based on communication (wiring) volume and heat removal considerations and discuss their numerical and asymptotic properties. We show that the bisection-bandwidth and bisection-inverse delay products—which are appropriate measures of performance for communication limited applications—are bounded from above for normally conducting layouts, whereas they may be arbitrarily increased for repeatered, optical and superconducting layouts. The latter two are shown to suffer slower growth rate of signal delay with increasing system size in 3 dimensions than repeatered interconnections and thus offer the best performance. Based on the considerations of this paper, the comparison between optical and superconducting interconnections for same dimensional layouts reduces to a comparison of their respective communication energies.

Keywords

Heat Removal Normal Conductor Optical Interconnection Connection Graph Increase System Size 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

List of Symbols

a

system radius in grid units

(area)

cross sectional area associated with each physical line

B

bit repetition rate along each edge of connection graph

c

vacuum velocity of light

C

capacitance per unit length

d

linear extent of a unit cell

dd

linear extent of an element

dtrans

linear extent of a transducer

e

Euclidean dimension of layout space

E

energy associated with each transmitted bit of information

f(∙)

functional form of connection flux distribution

g(∙)

functional form of line length distribution

h

height of dielectric

H

bisection

Jc

volume critical current density

Jsc

surface critical current density

k

number of graph edges per element

K

number of wiring tracks per cell

l

length of a line in real units

L

inductance per unit length

m

order of moment of line length distribution

M

number of wiring layers

n

fractal dimension of layout

N

number of elements

p

interConnectivity (Rent exponent) of layout

Q

maximum amount of power we can remove per cross section

r

length of a line in grid units

̄r

average connection length in grid units

<rm>

mth moment of line length distribution

R

resistance per unit length

Rd

drive impedance

R0C0

intrinsic delay of repeating devices

S

inverse of worst case signal delay

Save

inverse of average signal delay

t

height of conductor

T

minimum temporal pulse width associated with each transmitted bit of information

Sd

device imposed component of T

Te

line imposed component of T

Tp

propagation delay along a line

Tr

minimum pulse repetition interval along a line

V

nominal logic voltage level

w

width of conductor

(width)

transverse linear extent associated with each physical line

Z0

characteristic impedance

α

attenuation constant

ϰ

number of parallel physical lines used to establish each graph edge

δ

classical skin depth

ε

permittivity of dielectric

κ

coefficient for average connection length

λ

optical wavelength

λ

superconducting penetration depth

μ

permeability of dielectric

ρ

resistivity of conductor

τ

worst case signal delay

τave

average signal delay

υ

velocity of propagation

ω

fundamental frequency component

ξ

optimal number of repeater stages

ζm, ζ’m, ζ”m

coefficients for the moments of line length distribution

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    K. C. Saraswat and F. Mohammadi, Effect of scaling of interconnec-tions on the time delay of VLSI circuits, IEEE Transactions on Elec-tron Devices, vol. 29, pp. 645–650 (1982).CrossRefGoogle Scholar
  2. [2]
    D. S. Gardner, J. D. Meindl, and K. C. Saraswat, Interconnection and electromigration scaling theory, IEEE Transactions on Electron Devices, vol. 34, pp. 633–643 (1987).CrossRefGoogle Scholar
  3. [3]
    H. B. Bakoglu, Circuit and System Performance Limits on ULSI: In-terconnections and Packaging, PhD thesis, Stanford University, Stan-ford, California (1986).Google Scholar
  4. [4]
    H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addison-Wesley, Reading, Massachusetts (1990).Google Scholar
  5. [5]
    T. A. Schreyer, The Effects of Interconnection Parasitics on VLSI Performance, PhD thesis, Stanford University, Stanford, California (1989).Google Scholar
  6. [6]
    J. W. Goodman, F. J. Leonberger, S-Y. Kung, and R. Athale, Optical interconnections for VLSI systems, Proc. IEEE, vol. 72, pp. 850–866 (1984).CrossRefGoogle Scholar
  7. [7]
    W. D. Hillis, New computer architectures and their relationship to physics or why computer science is no good, Int. J. Theoretical Physics, vol. 21, pp. 255–262 (1982).CrossRefGoogle Scholar
  8. [8]
    R. W. Keyes, Communication in computation, Int. J. Theoretical Physics, vol. 21, pp. 263–273 (1982).CrossRefGoogle Scholar
  9. [9]
    A. C. Hartmann and J. D. Ullman, Model categories for theories of parallel systems, in Parallel Computing: Theory and Experience, G. J. Lipovski and M. Malek (Eds), John Wiley and Sons (1986).Google Scholar
  10. [10]
    R. K. Kostuk, J. W. Goodman, and L. Hesselink, Optical imaging ap-plied to microelectronic chip-to-chip interconnections, Applied Optics, vol. 24, pp. 2851–2858 (1985).CrossRefGoogle Scholar
  11. [11]
    M. R. Feldman, S. C. Esener, C. C. Guest, and S. H. Lee, Comparison between optical and electrical interconnects based on power and speed considerations, Applied Optics, vol. 27, pp. 1742–1751 (1988).CrossRefGoogle Scholar
  12. [12]
    M. R. Feldman, C. C. Guest, T. J. Drabik, and S. C. Esener, Com-parison between electrical and free space optical interconnects for fine grain processor arrays based on interconnect density capabilities, Ap-plied Optics, vol. 28, pp. 3820–3829 (1989).CrossRefGoogle Scholar
  13. [13]
    P.R. Haugen, S. Rychnovsky, A. Husain, and L. D. Hutcheson, Optical interconnects for high speed computing, Optical Engineering, vol. 25, p. 1076 (1986).Google Scholar
  14. [14]
    D. A. B. Miller, Optics for low-energy communication inside digital processors: Quantum detectors, sources and modulators as efficient impedance converters, Optics Letters, vol. 14, pp. 146–148 (1989).CrossRefGoogle Scholar
  15. [15]
    R. C. Frye, Analysis of the trade-offs between conventional and su-perconducting interconnections, IEEE Circuits and Devices Magazine, pp. 27–32 (May 1989).Google Scholar
  16. [16]
    H. Kroger, C. Hilbert, U. Ghoshal, D. Gibson, and L. Smith, Appli-cations of superconductivity to packaging, IEEE Circuits and Devices Magazine, pp. 16–21 (May 1989).Google Scholar
  17. [17]
    O. K. Kwon, B. W. Langley, R. F. W. Pease, and M. R. Beasley, Superconductors as very high-speed system-level interconnects, IEEE Electron Device Letters, vol. 8, pp. 582–585 (1987).CrossRefGoogle Scholar
  18. [18]
    J. D. Ullman, Computational Aspects of VLSI, Computer Science Press, Rockville, Maryland (1984).zbMATHGoogle Scholar
  19. [19]
    C. E. Leiserson, Area-Efficient VLSI Computation, The MIT Press, Cambridge, Massachusetts (1983).Google Scholar
  20. [20]
    R. R. Tummala and E. J. Rymaszewski (Eds), Microelectronics Pack-aging Handbook, Van Nostrand Reinhold, New York, New York (1989).Google Scholar
  21. [21]
    C. Berge, The Theory of Graphs, Wiley, New York (1962).zbMATHGoogle Scholar
  22. [22]
    W. E. Donath, Placement and average interconnection lengths of com-puter logic, IEEE Transactions on Circuits and Systems, vol. 26, pp. 272–277 (1979).zbMATHCrossRefGoogle Scholar
  23. [23]
    B. S. Landman and R. L. Russo, On a pin versus block relationship for partitions of logic graphs, IEEE Transactions on Computers, vol. 20, pp. 1469–1479 (1971).CrossRefGoogle Scholar
  24. [24]
    R. L. Russo, On the tradeoff between logic performance and circuit-to-pin ratio for LSI, IEEE Transactions on Computers, vol. 21, pp. 147–153 (1972).CrossRefGoogle Scholar
  25. [25]
    W. E. Donath, Stochastic model of the computer logic design process, Technical Report RC 3136, IBM Thomas T.J.Watson Research Center, Yorktown Heights, New York (1970).Google Scholar
  26. [26]
    W. E. Donath, Equivalence of memory to ‘random logic’, IBM Journal of Research and Development, vol. 18, pp. 401–407 (1974).MathSciNetzbMATHCrossRefGoogle Scholar
  27. [27]
    L. Pietronero, Fractals in physics: Introductory concepts, in S. Lundqvist, N. H. March, and M. P. Tosi (Eds), Order and Chaos in Nonlinear Physical Systems, Plenum Press, New York (1988).Google Scholar
  28. [28]
    B. B. Mandelbrot, Fractals: Form, Chance and Dimension, W.H. Freeman, San Francisco (1977).zbMATHGoogle Scholar
  29. [29]
    R. W. Keyes, The Physics of VLSI Systems, Addison-Wesley, Reading, Massachusetts (1987).Google Scholar
  30. [30]
    W. E. Donath, Wire length distribution for placements of computer logic, IBM Journal of Research and Development, vol. 25, pp. 152–155 (1981).CrossRefGoogle Scholar
  31. [31]
    M. Feuer, Connectivity of random logic, IEEE Transactions on Com-puters, vol. 31, pp. 29–33 (1982).CrossRefGoogle Scholar
  32. [32]
    P. Christie and S. B. Styer, Fractal description of computer intercon-nection distributions, in S. K. Tewksbury and J. Carruthers (Eds), Microelectronic Interconnects and Packaging: System and Process In-tegration, volume 1390. SPIE (1990).Google Scholar
  33. [33]
    P. Christie, J. E. Cotter, and A. M. Barrett, Design and simulation of optically interconnected computer systems, in A. P. DeFonzo (Ed), In-terconnection of High Speed and High Frequency Devices and Systems, volume 947, pp. 19–24. SPIE (1989).Google Scholar
  34. [34]
    B. B. Mandelbrot, The Fractal Geometry of Nature, W.H. Freeman, New York (1983).Google Scholar
  35. [35]
    B. B. Mandelbrot, Information theory and psycholinguistics: A the-ory of word frequencies, in P. F. Lazarsfeld and N. W. Henry (Eds), Readings in Mathematical Social Science, MIT press, Cambridge, Massachusetts (1968).Google Scholar
  36. [36]
    B. B. Mandelbrot, The Pareto-Levy law and the distribution of income, International Economic Review, vol. 1, pp. 79–106 (1960).zbMATHCrossRefGoogle Scholar
  37. [37]
    A. C. Hartmann, Computational metrics and fundamental limits for parallel architectures, in S. K. Tewksbury (Ed), Frontiers of Computing Systems Research, Volume 1, Plenum Press, New York (1990).Google Scholar
  38. [38]
    A. El Gamal, J. L. Kouloheris, D. How, and M. Morf, BiNMOS: A basic cell for BiCMOS sea-of-gates, in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 8.3.1–8.3.4 (1989).Google Scholar
  39. [39]
    R. W. Keyes, The wire-limited logic chip, IEEE Journal of Solid State Circuits, vol. 17, pp. 1232–1233 (1982).CrossRefGoogle Scholar
  40. [40]
    W. R. Heller, W. F. Mikhail, and W. E. Donath, Prediction of wiring space requirements for LSI, Journal of Design Automation and Fault Tolerant Computing, vol. 2, pp. 117–144 (1978).Google Scholar
  41. [41]
    A. El Gamal, Two-dimensional stochastic model for interconnections in master slice integrated circuits, IEEE Transactions on Circuits and Systems, vol. 28, pp. 127–134 (1981).zbMATHCrossRefGoogle Scholar
  42. [42]
    A. Orlitsky and A. El Gamal, Communication complexity, in Y. S. Abu-Mostafa (Ed), Complexity in Information Theory, Springer-Verlag, New York (1988).Google Scholar
  43. [43]
    R. Barakat and J. Reif, Lower bound on the computational efficiency of optical computing systems, Applied Optics, vol. 26, pp. 1015–1018 (1987).CrossRefGoogle Scholar
  44. [44]
    H. Kogelnik, Theory of optical waveguides, in T. Tamir (Ed), Guided-Wave Optoelectronics, Springer-Verlag, Berlin Heidelberg (1988).Google Scholar
  45. [45]
    A. Yariv, Introduction to Optical Electronics, Second Edition, Holt, Rinehart and Winston, New York (1976).Google Scholar
  46. [46]
    H. M. Ozaktas and J. W. Goodman, Lower bound for the communi-cation volume required for an optically interconnected array of points, Journal of the Optical Society of America A, vol. 7, pp. 2100–2106 (1990).CrossRefGoogle Scholar
  47. [47]
    R. F. Thompson, The Brain, W.H. Freeman and Company, New York (1985).Google Scholar
  48. [48]
    H. M. Ozaktas, Y. Amitai, and J. W. Goodman, Comparison of sys-tem size for some optical interconnection architectures and the folded multi-facet architecture, Optics Communications (1991 — accepted for publication).Google Scholar
  49. [49]
    M R. Feldman and C. C. Guest, Interconnect density capabilities of computer generated holograms for optical interconnection of very large scale integrated circuits, Applied Optics, vol. 28, pp. 3134–3137 (1989).CrossRefGoogle Scholar
  50. [50]
    H. M. Ozaktas, H. Oksuzoglu, R. F. W. Pease, and J. W. Goodman, The effect on scaling of heat removal requirements in 3 dimensional systems, Submitted to IEEE Electron Device Letters, 1990.Google Scholar
  51. [51]
    D. B. Tuckerman and R. F. W. Pease, High performance heat sinking for VLSI, IEEE Electron Device Letters, vol. 2, pp. 126–129 (1981).CrossRefGoogle Scholar
  52. [52]
    T. L. Michalka, Models for Wafer Scale Integration Implementation, PhD thesis, Stanford University, Stanford, California (1988).Google Scholar
  53. [53]
    P. M. Solomon, A comparison of semiconductor devices for highspeed logic, Proc. IEEE, vol. 70, pp. 489–509 (1982).CrossRefGoogle Scholar
  54. [54]
    A. Masaki, Electrical resistance as a limiting factor for high perfor-mance computer packaging, IEEE Circuits and Devices Magazine, pp. 22–26 (May 1989).Google Scholar
  55. [55]
    J. T. Watt and J. D. Plummer, Effect of interconnection delay on liquid nitrogen temperature CMOS circuit performance, Proceedings of the International Electron Devices Meeting, pp. 393–396 (1987).Google Scholar
  56. [56]
    R E. Matick, Transmission Lines for Digital and Communication Net-works, Mc-Graw Hill, New York (1969).Google Scholar
  57. [57]
    S. Ramo, J. R. Whinnery, and T. Van Duzer, Fields and Waves in Communication Electronics, John Wiley and Sons Inc., New York, second edition (1984).Google Scholar
  58. [58]
    A. J. Blodgett Jr., Microelectronic packaging, Scientific American, vol. 249, pp. 86–96 (July 1983).CrossRefGoogle Scholar
  59. [59]
    R. W. Keyes, Physical limits in digital electronics, Proc. IEEE, vol. 63, pp. 740–767 (1975).CrossRefGoogle Scholar
  60. [60]
    R. W. Keyes, Fundamental limits in digital information processing, Proc. IEEE, vol. 69, pp. 267–278 (1981).CrossRefGoogle Scholar
  61. [61]
    R. W. Keyes, The evolution of digital electronics towards VLSI, IEEE Transactions on Electron Devices, vol. 26, pp. 271–279 (1979).CrossRefGoogle Scholar
  62. [62]
    R. W. Keyes, A figure of merit for IC packaging, IEEE Journal of Solid State Circuits, vol. 13, pp. 265–266 (1978).CrossRefGoogle Scholar
  63. [63]
    H. B. Bakoglu and J. D. Meindl, Optimal interconnection circuits for VLSI, IEEE Transactions on Electron Devices, vol. 32, pp. 903–909 (1985).CrossRefGoogle Scholar
  64. [64]
    O-K. Kwon, Chip-to-Chip Interconnections for Very High-speed System-level Integration, PhD thesis, Stanford University, Stanford, California (1988).Google Scholar
  65. [65]
    H. H. Zappe, Josephson quantum interference computer devices, IEEE Transactions on Magnetics, vol. 13, pp. 41–47 (1977).CrossRefGoogle Scholar
  66. [66]
    H. J. Caulfield and J. Shamir, Wave particle duality considerations in optical computing, Applied Optics, vol. 28, pp. 2184–2186 (1989).CrossRefGoogle Scholar
  67. [67]
    J. Hopcroft, W. Paul, and L. Valiant, On time versus space, Journal of the Association for Computing Machinery, vol. 24, pp. 332–337 (1977).MathSciNetzbMATHCrossRefGoogle Scholar
  68. [68]
    W. D. Hillis, The Connection Machine, The MIT press, Cambridge, Massachusetts (1985).Google Scholar
  69. [69]
    M. R. Feldman and C. C. Guest, Nested crossbar connection networks for optically interconnected processor arrays for vector-matrix multi-plication, Applied Optics, vol. 29, pp. 1068–1076 (1990).CrossRefGoogle Scholar
  70. [70]
    H. M. Ozaktas and J. W. Goodman, Optimal partitioning of very large scale optoelectronic computing systems, Optical Society of America 1990 Annual Meeting Technical Digest (1990).Google Scholar
  71. [71]
    H. M. Ozaktas and J. W. Goodman, Multiplexed hybrid interconnection architectures, Proceedings of the 1991 OSA Topical Meeting on Optical Computing (1991).Google Scholar
  72. [72]
    J. W. Goodman, Fan-in and fan-out with optical interconnections, Op-tica Acta, vol. 32, p. 1489 (1985).CrossRefGoogle Scholar
  73. [73]
    C.D. Thompson, Area-time complexity for VLSI, Proceedings of the 11th Annual ACM Symposium on the Theory of Computing, pp. 81–88 (1979).Google Scholar

Copyright information

© Plenum Press, New York 1991

Authors and Affiliations

  • Haldun M. Ozaktas
    • 1
  • Joseph W. Goodman
    • 1
  1. 1.Information Systems Laboratory, Durand Building, Department of Electrical EngineeringStanford UniversityStanfordUSA

Personalised recommendations