Port Delays

  • Sridhar Gangadharan
  • Sanjay Churiwala


Once the clock constraints have been applied, all the register to register paths can be timed. Now, the delay constraints have to be applied on non-clock ports. If input and output port constraints are not specified, timing analysis tools assume a highly optimistic timing requirements on the interfaces. They assume the combinational logic inside the block can have the entire period to itself and leave nothing for the portion of the signal outside the block.


Timing Analysis Tool Rising Clock Edge Clock Latency Clock Uncertainty Input Delay 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Sridhar Gangadharan
    • 1
  • Sanjay Churiwala
    • 2
  1. 1.Atrenta, Inc.San JoseUSA
  2. 2.XilinxHyderabadIndia

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