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Other Clock Characteristics

  • Sridhar Gangadharan
  • Sanjay Churiwala
Chapter
  • 2.8k Downloads

Abstract

In the preceding chapters, we assumed the clock to be ideal, i.e., they transition from 0 to 1 and vice versa instantaneously (have a rectangular waveform); they reach all the flops in the design at the same time (all edges align) and there is no delay between the clock generation circuit and the place where the clock is actually consumed. In reality, clocks are never ideal.

Keywords

Clock Generation Circuit Capture Clock Clock Path Falling Edge Clock Network 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Sridhar Gangadharan
    • 1
  • Sanjay Churiwala
    • 2
  1. 1.Atrenta, Inc.San JoseUSA
  2. 2.XilinxHyderabadIndia

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