Other Clock Characteristics

  • Sridhar Gangadharan
  • Sanjay Churiwala


In the preceding chapters, we assumed the clock to be ideal, i.e., they transition from 0 to 1 and vice versa instantaneously (have a rectangular waveform); they reach all the flops in the design at the same time (all edges align) and there is no delay between the clock generation circuit and the place where the clock is actually consumed. In reality, clocks are never ideal.


Clock Generation Circuit Capture Clock Clock Path Falling Edge Clock Network 
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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Sridhar Gangadharan
    • 1
  • Sanjay Churiwala
    • 2
  1. 1.Atrenta, Inc.San JoseUSA
  2. 2.XilinxHyderabadIndia

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